数字系统设计 - DFT与芯片测试设计

测试

Testing2ZDMC–Lec.#22DesignMethodologyinDetailDesignPartitionDesignEntryBehavioralModelingSimulation/FunctionalVerificationPre-SynthesisSign-OffSynthesizeandMapGate-levelNetListPostsynthesisDesignValidationPostsynthesisTimingVerificationTestGenerationandFaultSimulationCellPlacement/ScanInsertation/RoutingVerifyPhysicalandElectricalRulesSynthesizeandMapGate-levelNetListDesignIntegrationAndVerificationDesignSign-OffDesignSpecification3ZDMC–Lec.#22TestingofLogicCircuitsFaultModels(故障模型)TestGenerationandCoverageFaultDetectionDesignforTest（可测试性设计）4ZDMC–Lec.#22FaultModel(故障模型)Stuck-AtModel（固定型故障模型）Assumeselectedwires(gateinputoroutput)are“stuckat”logicvalue0or1Modelscurtainkindsoffabricationflawsthatshortcircuitwirestogroundorpower,orbrokenwiresthatarefloatingWirewstuck-at-0:w/0Wirewstuck-at-1:w/1Oftenassumethereisonlyonefaultatatime—eventhoughinrealcircuitsmultiplesimultaneousfaultsarepossibleandcanmaskeachotherObviouslyaverysimplisticmodel!5ZDMC–Lec.#22FaultModelSimpleexample:Generateatestcasetodetermineifaisstuckat1Try000Ifastuckat1,expecttoseef=0,butsee1insteadw1w2w3a/1bcdf0000see1butshouldbe06ZDMC–Lec.#22FaultModel(故障模型)Simpleexamplew1w2w3abcdfTestw1w2w3000001010011100101110111a/0X

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XFaultDetectedTestSet7ZDMC–Lec.#22ProblemswithFaultModelIngeneral,n-inputcircuitsrequiremuchlessthan2ntestinputstocoverallpossiblestuck-at-faultsinthecircuitHowever,thisnumberisusuallystilltoolargeinrealcircuitsforpracticalpurposesFindingminimumtestcoverisanNP-hardproblemtoo8ZDMC–Lec.#22PathSensitization（路径敏化）Wire-at-timetestingtoolaboriousBettertofocusonwiringpaths,enablingmulti-wiretestingatthesametime“Activate”apathsothatchangesinsignalpropagatingalongthepathaffectstheoutput9ZDMC–Lec.#22PathSensitization（路径敏化）SimpleExample:Toactivatethepath,setinputssothatw1caninfluencefE.g.,w2=1,w3=0,w4=1ANDgates:oneinputat1passestheotherinputNORgates:oneinputat0invertstheotherinputTotest:w1setto1shouldgeneratef=0ifpathokfaultsa/0,b/0,c/1causef=1w1setto0shouldgeneratef=1ifpathokfaultsa/1,b/1,c/0causef=0Onetestcancaptureseveralfaultsatonce!w1w2bfcaw3w410110ZDMC–Lec.#22PathSensitizationGoodnews:onetestchecksforseveralfaultsNumberofpathsmuchsmallerthannumberofwiresStillanimpracticallylargenumberofpathsforlarge-scalecircuitsPathideacanbeusedto“propagate”afaulttotheoutputtoobservethefaultSetinputsandintermediatevaluessoastopassaninternalwiretotheoutputwhilesettinginputstodrivethatinternalwiretoaknownvalueIfpropagatedvalueisn’tasexpected,thenwehavefoundafaultontheisolatedwire11ZDMC–Lec.#22FaultPropagationw1w2bfcgw3w4hkw1w2fw3w4b/001111DD00D12ZDMC–Lec.#22FaultPropagationw1w2bfcgw3w4hkw1w2fDw3w4g/1110000DDD13ZDMC–Lec.#22TreeStructuredCircuitsTotestinputsstuck-at-0atgivenANDgateSetinputsatothergatestogenerateANDoutputofzeroForceinputsatselectedgatetogenerateaoneIffis1thencircuitok,elsefaultTotestinputsstuck-at-1atgivenANDgateDriveinputtotestto0,restofinputsdrivento1Othergatesdrivenwithinputsthatforcegatesto0Iffis0thenOK,elsefault.w1w3w4w2w3w4w1w2w3f14ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest111010000000Stuck-at-0015ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest010111110000Stuck-at-0016ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest000101111000Stuck-at-0017ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110100Stuck-at-1118ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110010Stuck-at-1119ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest011110110001Stuck-at-1120ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest101100011100Stuck-at-1121ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest101100011001Stuck-at-1122ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest110011000010Stuck-at-11Anyotherstuck-at-1casescovered?23ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest100101011010Stuck-at-11Anyotherstuck-at-1casescovered?Wasthatcasealreadycovered?24ZDMC–Lec.#22TreeStructuredCircuitsw1w3w4w2w3w4w1w2w3f12345678w110001110w311010100w410011000w201111010w311010100w401100111w101110001w201111010w300101011w110001110w201111010w300101011w401100111Stuck-at-0Stuck-at-1ProductTermTest000001101001Stuck-at-11Allinputsstuck-at-1’scoverednow25ZDMC–Lec.#22RandomTestingSofar:deterministictestingAlternative:randomtestingGeneraterandominputpatternstodistinguishbetweenthecorrectfunctionandthefaultyfunctionNumberofTestsProbabilityFaultDetectedSmallnumberoftests

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thefault26ZDMC–Lec.#22SequentialTestingDuetoembeddedstateinsideflip-flops,itisdifficulttoemploythesamemethodsaswithcombinationallogicAlternativeapproach:designfortestScanPathtechnique:FFinputspassthroughmultiplexerstagestoallowthemtobeusedinnormalmodeaswellasaspecialtestshiftregistermode27ZDMC–Lec.#22ScanPathTechniqueConfigureFFsintoshiftregistermode(redpath)Scanintestpatternof0sand1sNon-stateinputscanalsobeonthescanpath(thinksynchronousMealyMachine)Runsystemforoneclockcyclein“normal”mode(blackpath)—nextstatecapturedinscanpathReturntoshiftregistermodeandshiftoutthecapturedstateandoutputsCombinationalLogic28ZDMC–Lec.#22ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFszY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S029ZDMC–Lec.#22ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFszY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S10000033ZDMC–Lec.#22ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFsNormalw=0Outputz=0,Y1=0,Y2=0ObservezdirectlyzY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S00000034ZDMC–Lec.#22ScanPathExamplew,y1,y2testvector001Scan01intoy1,y2FFsNormalw=0Outputz=0,Y1=0,Y2=0ObservezdirectlyScanoutY1,Y2zY1Y2DQQDQQ

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01y1y2wScan-inScan-outG/S00036ZDMC–Lec.#22Built-inSelf-Test(BIST)TestVectorGeneratorPseudorandomtestswithafeedbackshiftregisterSeedgeneratesasequenceoftestpatternsOutputscombinedusingthesametechniqueGeneratesauniquesignaturethatcanbecheckedtodetermineifthecircuitiscorrectTestVectorGeneratorCircuitUnderTestTestResponseCompressorx0...xn-1P0...Pm-1Signature37ZDMC–Lec.#22LinearFeedbackShiftRegisterDQQDQQDQQDQQDQQDQQDQQDQQPSignatureRandomTestPatternInputfrom

circuitundertest38ZDMC–Lec.#22LinearFeedbackShiftRegisterStartingwiththepattern1000,generates15differentpatternsinsequenceandthenrepeatsPattern0000isano-noDQQDQQDQQDQQx3x2x1x0x3x2x1x0ff10001110011110111110011111011001011101011101001100001111001001000001000001110001……InitialConfiguration39ZDMC–Lec.#22LinearFeedbackShiftRegisterMulti-inputCompressorDQQDQQP3P2DQQP1DQQP0SignatureCircuitUnderTestOutputs40ZDMC–Lec.#22CompleteSelf-TestSystemCombinationalCircuitFFsandMuxesMICSICScanoutPRBSGScaninMUXPRBSGNormalInputsRandomTest

SequencesMulti-inputCompressorRandomTest

SequencesSingle-inputCompressor41ZDMC–Le