组成原理第六章risc cpu设计实例v1 2014

RISC

CPU

设计实例一个简单的RISC总体结构如下图所示。Load_R0Load_R1Load_R2Load_R3Load_PCInc_PCSel_Bus_1_MuxLoad_IRLoad_Add_RegLoad_Reg_YLoad_Reg_ZZeroSel_Bus_2_MuxRISC_SPMR0R1R2R30

1

2

3

4Mux_1Reg_Y0

1

2Mux_1Add_RBus_1ALUalu_zero_flagReg_ZZflagBus_2writemem_wordRISC_SPM是一个存储程序的RISC CPU，由三个功能单元构成：处理器、控制器和存储器。指令从存储器中提取、译码和执行，完成：对算术逻辑单元（ALU）中的数据进行操作；改变寄存器中的内容；改变程序计数器（

PC）、指令寄存器（

IR）和地址寄存器（ADD_R）中的内容；改变存储器中的内容；检索存储器中的数据和指令；控制数据在系统总线中的移动。RISC

CPU

设计实例RISC_SPM：处理器处理器包括寄存器、数据通道、控制线，以及能按照保存在指令寄存器中的操作码对ALU的操作数进行算术与逻辑操作的ALU。第一个多路复用器Mux_1决定送往Bus_1的数据源；第二个多路复用器Mux_2决定送往Bus_2的数据源。RISC_SPM：ALUALU有两个操作数数据通道，data_1和data_2，它的指令集仅限于

ADD、SUB、AND和NOT。RISC

CPU

设计实例RISC_SPM：控制器所有动作的时序都由控制器决定。控制器根据要执行的指令把数据传送到目的地。因此，控制器的设计完全依赖于ALU的技术指标、数据通道资源和可利用的时钟方案。控制单元的作用：决定何时装载寄存器；选择数据通过多路选择器的数据通道；决定何时将数据写入存储器中；控制该结构中的三态总线。RISC

CPU

设计实例RISC_SPM：指令集CPU由机器语言程序控制，该程序是由存储在存储器中的指令集组成的。因此，控制器的设计除了依赖于数据通路的结构外，还依赖于处理器的指令集（也就是程序所执行的指令）。单字节指令：NOP、ADD、AND、NOT、SUB两字节指令：RD、WR、BR、BRZRISC

CPU

设计实例RISC_SPM：控制器设计控制器可以设计成一个有限状态机（FSM）。在给定结构图、指令集及设计中所用的定时方式的情况下，还必须指定状态机的状态。状态机有三个操作阶段：取指令、译码和执行。取指令阶段是从存储器中得到指令；译码阶段是编译指令、控制数据通道和装载寄存器；执行是产生指令的结果。取指令阶段需要两个时钟周期，一个时钟周期用来装载地址寄存器，另一个时钟周期用来从存储器中得到给定地址的数据字。译码阶段在一个时钟周期内完成。执行阶段可能需要0个、1个或2个以上的时钟周期，这主要取决于所执行的指令。RISC

CPU

设计实例RISC_SPM：控制器设计（继）RISC_SPM控制器共有12个状态：S_idle：当复位有效时进入的状态，不执行任何操作；S_fet1：把程序计数器中的内容装入地址寄存器；S_fet2：将地址寄存器指定地址中的数据字装入指令寄存器；S_dec：对指令寄存器译码，产生控制数据通道和寄存器传输的信号；S_ex1：对于单字节指令，执行ALU操作；S_rd1：将RD指令的第二字节装入地址寄存器，并增加PC值；S_rd2：用S_rd1中所装载地址中的数据来装载目的寄存器；S_wr1：将WR指令的第二字节装入地址寄存器，并增加PC值；S_wr2：用S_wr1中所装载地址中的数据来装载目的寄存器；S_br1：将BR指令的第二字节装入地址寄存器，并增加PC值；S_br2：用S_br1中所装载地址中的数据来装载PC；S_halt：捕获有效指令编码失败的默认状态。RISC

CPU

设计实例RISC_SPM：控制器设计（继）RISC

CPU

设计实例RISC

CPU

设计实例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IRInc_PC2S_dec3NOPWRSel_PCSel_Bus_1Load_Add_RS_wr1/Sel_MemLoad_Add_RInc_PC7src=R0src=R1src=R2Sel_R0writeS_wr28Sel_R1writeSel_R2writeSel_R3writeRISC

CPU

设计实例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IRInc_PC2S_dec3NOPNOTsrc=R0src=R1src=R2Sel_R0Sel_Bus_1Sel_R1Sel_Bus_1Sel_R2Sel_Bus_1Sel_R3Sel_Bus_1dest=R0dest=R1dest=R2Sel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZSel_ALULoad_R0Load_Reg_ZRISC

CPU

设计实例S_idle0rstS_fet1/Sel_PCSel_Bus_1Load_Add_R1S_fet2/Sel_MemLoad_IR

Inc_PC2S_dec3NOPBRBRZzeroSel_PCSel_Bus_1Load_Add_RS_br210Sel_MemLoad_PCInc_PCS_br1/Sel_MemLoad_Add_R9S_halt11RISC

CPU

设计实例module

RISC_SPM

(clk,

rst);parameter

word_size

=

8;parameter

Sel1_size

=

3;parameter

Sel2_size

=

2;wire

[Sel1_size-1:

0]

Sel_Bus_1_Mux;wire

[Sel2_size-1:

0]

Sel_Bus_2_Mux;input

clk,

rst;//

Data

Netswire

zero;wire

[word_size-1:

0]

instruction,

address,

Bus_1,

mem_word;//

Control

Netswire

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,

Load_IR;wire

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z;wire

write;Processing_Unit

M0_Processor

(instruction,

zero,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,Load_R2,

Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,Load_Reg_Z,

Sel_Bus_2_Mux,

clk,

rst);Control_Unit

M1_Controller

(Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,Sel_Bus_1_Mux,Sel_Bus_2_Mux

,

Load_IR,Load_Add_R,Load_Reg_Y,

Load_Reg_Z,write,

instruction,

zero,

clk,

rst);Memory_Unit

M2_SRAM

(

.data_out(mem_word),

.data_in(Bus_1),

.address(address),.clk(clk),

.write(write)

);endmoduleRISC

CPU

设计实例module

Processing_Unit

(instruction,

Zflag,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,

Load_R2,Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z,Sel_Bus_2_Mux,clk,

rst);parameter

word_size

=

8;parameter

op_size

=

4;parameter

Sel1_size

=

3;parameter

Sel2_size

=

2;output

[word_size-1:

0]outputinput

[word_size-1:

0]inputinput[Sel1_size-1:

0]input[Sel2_size-1:

0]inputinputwirewire

[word_size-1:

0]wire

[word_size-1:

0]wire

[word_size-1:

0]wirewire

[op_size-1

:

0]instruction,

address,

Bus_1;Zflag;mem_word;Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC;Sel_Bus_1_Mux;Sel_Bus_2_Mux;Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z;clk,

rst;Load_R0,

Load_R1,

Load_R2,

Load_R3;Bus_2;R0_out,

R1_out,

R2_out,

R3_out;PC_count,

Y_value,

alu_out;alu_zero_flag;opcode

=

instruction

[word_size-1:

word_size-op_size];RISC

CPU

设计实例module

Processing_Unit

(instruction,

Zflag,

address,

Bus_1,

mem_word,

Load_R0,

Load_R1,

Load_R2,Load_R3,

Load_PC,

Inc_PC,

Sel_Bus_1_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,Load_Reg_Z,Sel_Bus_2_Mux,clk,

rst);（续）Register_UnitR0(R0_out,

Bus_2,

Load_R0,

clk,

rst);Register_UnitR1(R1_out,

Bus_2,

Load_R1,

clk,

rst);Register_UnitR2(R2_out,

Bus_2,

Load_R2,

clk,

rst);Register_UnitR3(R3_out,

Bus_2,

Load_R3,

clk,

rst);Register_UnitReg_Y(Y_value,

Bus_2,

Load_Reg_Y,

clk,

rst);D_flopReg_Z(Zflag,

alu_zero_flag,

Load_Reg_Z,

clk,rst);Address_RegisterAdd_R(address,

Bus_2,

Load_Add_R,

clk,

rst);Instruction_RegisterIR(instruction,

Bus_2,

Load_IR,

clk,

rst);Program_CounterPC(PC_count,

Bus_2,

Load_PC,

Inc_PC,

clk,

rst);Multiplexer_5chMux_1(Bus_1,

R0_out,

R1_out,

R2_out,

R3_out,

PC_count,

Sel_Bus_1_Mux);Multiplexer_3chMux_2(Bus_2,

alu_out,

Bus_1,

mem_word,

Sel_Bus_2_Mux);(alu_zero_flag,

alu_out,

Y_value,

Bus_1,opcode);Alu_RISC

ALUendmoduleRISC

CPU

设计实例module

Register_Unit

(data_out,

data_in,

load,

clk,

rst);parameteroutput

[word_size-1:

0][word_size-1:

0]inputinputinputreg[word_size-1:

0]word_size

=

8;data_out;data_in;load;clk,rst;data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmodulemodule

D_flop

(data_out,

data_in,

load,

clk,

rst);outputinputinputinputregdata_out;data_in;load;clk,rst;data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load

==

1)data_out

<=

data_in;endmoduleRISC

CPU

设计实例module

Address_Register

(data_out,

data_in,

load,

clk,rst);parameter

word_size

=8;output

[word_size-1:

0]

data_out;input[word_size-1:

0]data_in;inputload,

clk,

rst;reg[word_size-1:

0]data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmodulemodule

Instruction_Register(data_out,

data_in,

load,

clk,

rst);parameter

word_size

=8;output

[word_size-1:

0]

data_out;input[word_size-1:

0]data_in;inputload;inputclk,rst;reg[word_size-1:

0]data_out;always

@

(posedgeclkor

negedgerst)if(rst

==

0)

data_out

<=

0;

else

if

(load)

data_out

<=

data_in;endmoduleRISC

CPU

设计实例module

Program_Counter

(count,

data_in,

Load_PC,

Inc_PC,

clk,

rst);parameter

word_size

=8;output

[word_size-1:

0]

count;input[word_size-1:

0]data_in;inputLoad_PC,

Inc_PC;inputclk,rst;reg[word_size-1:

0]count;always

@

(posedgeclkor

negedgerst)if

(rst

==

0)

count

<=0;

else

if

(Load_PC)

count<=data_in;else

if

(Inc_PC)count<=count+1;endmoduleRISC

CPU

设计实例module

Multiplexer_5ch

(mux_out,

data_a,data_b,

data_c,

data_d,

data_e,sel);parameter

word_size

=8;output

[word_size-1:

0]mux_out;data_a,

data_b,

data_c,data_d,data_e;inputinput[word_size-1:

0][2:

0]

sel;?data_a:(sel

==1)assign

mux_out=(sel

==0)?

data_b

:

(sel

==

2)?

data_c:

(sel

==

3)?

data_d

:

(sel

==

4)?

data_e

:

'bx;endmodulemodule

Multiplexer_3ch

(mux_out,

data_a,

data_b,

data_c,

sel);parameterword_size

=

8;output[word_size-1:

0]mux_out;input[word_size-1:

0]data_a,

data_b,

data_c;input[1:

0]

sel;assign

mux_out

=

(sel

==

0)

?

data_a:

(sel

==

1)

?

data_b

:

(sel

==

2)

?

data_c:

'bx;endmoduleRISC

CPU

设计实例module

Alu_RISC

(alu_zero_flag,

alu_out,

data_1,

data_2,

sel);parameter

word_size

=

8;parameter

op_size

=

4;//

Opcodes=4'b0000;=4'b0001;=4'b0010;=4'b0011;=4'b0100;parameter

NOPparameter

ADDparameter

SUBparameter

ANDparameter

NOTparameter

RDparameter

WRparameter

BRparameter

BRZoutputoutput

[word_size-1:

0]input

[word_size-1:

0]input

[op_size-1:

0]reg

[word_size-1:

0]=

4'b0101;=4'b0110;=

4'b0111;=4'b1000;alu_zero_flag;alu_out;data_1,

data_2;sel;alu_out;assign

alu_zero_flag

=~|alu_out;always

@

(sel

or

data_1

or

data_2)case

(sel)NOP: alu_out

=

0;ADD:SUB:AND:alu_out

=

data_1

+

data_2;

//

Reg_Y

+

Bus_1alu_out

=

data_2

-

data_1;alu_out

=

data_1

&

data_2;NOT: alu_out

=

~

data_2;//

Gets

data

from

Bus_1default:

alu_out

=

0;endcaseendmoduleRISC

CPU

设计实例module

Control_Unit

(

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC,Sel_Bus_1_Mux,

Sel_Bus_2_Mux,

Load_IR,

Load_Add_R,

Load_Reg_Y,

Load_Reg_Z,write,

instruction,

zero,

clk,

rst);parameter

word_size

=

8,

op_size

=

4,

state_size

=4;parameter

src_size

=

2,

dest_size

=

2,

Sel1_size

=

3,

Sel2_size

=

2;//

State

Codesparameter

S_idle

=

0,

S_fet1

=

1,

S_fet2

=

2,

S_dec

=3;parameter

S_ex1

=

4,

S_rd1

=

5,

S_rd2

=6;parameter

S_wr1

=

7,

S_wr2

=

8,

S_br1

=

9,

S_br2

=

10,

S_halt

=

11;//

Opcodesparameter

NOP

=

0,

ADD

=

1,

SUB

=2,

AND

=

3,

NOT

=

4;parameter

RD

=

5,

WR

=

6,

BR

=

7,

BRZ=

8;//

Source

and

Destination

Codesparameter

R0

=

0,

R1

=

1,

R2

=

2,

R3

=

3;output

Load_R0,

Load_R1,

Load_R2,

Load_R3;output

Load_PC,

Inc_PC;output

[Sel1_size-1:0]

Sel_Bus_1_Mux;output

Load_IR,

Load_Add_R;output

Load_Reg_Y,

Load_Reg_Z;output

[Sel2_size-1:

0]

Sel_Bus_2_Mux;output

write;input

[word_size-1:

0]

instruction;input

zero;input

clk,

rst;RISC

CPU

设计实例reg

[state_size-1:

0]

state,

next_state;reg

Load_R0,

Load_R1,

Load_R2,

Load_R3,

Load_PC,

Inc_PC;reg

Load_IR,

Load_Add_R,

Load_Reg_Y;reg

Sel_ALU,

Sel_Bus_1,

Sel_Mem;reg

Sel_R0,

Sel_R1,

Sel_R2,

Sel_R3,

Sel_PC;reg

Load_Reg_Z,

write;reg

err_flag;wire

[op_size-1:0]

opcode

=

instruction

[word_size-1:

word_size

-

op_size];wire

[src_size-1:

0]

src

=

instruction

[src_size

+

dest_size

-1:

dest_size];wire

[dest_size-1:0]

dest

=

instruction

[dest_size

-1:0];//

Mux

selectorsassign

Sel_Bus_1_Mux[Sel1_size-1:0]

=

Sel_R0

?

0:Sel_R1

?

1:Sel_R2

?

2:Sel_R3

?

3:Sel_PC

?

4:

3'bx;

//

3-bits,

sized

numberassign

Sel_Bus_2_Mux[Sel2_size-1:0]

=

Sel_ALU

?

0:Sel_Bus_1

?

1:Sel_Mem

?

2:

2'bx;always

@

(posedge

clk

or

negedge

rst)

begin:

State_transitionsif

(rst

==

0)

state

<=

S_idle;

else

state

<=

next_state;

endRISC

CPU

设计实例always

@

(state

or

opcode

or

zero)

begin:

Output_and_next_stateSel_R0

=

0;

Sel_R1

=

0;Sel_R2

=

0;Sel_R3

=

0;Sel_PC

=0;Load_R0

=

0;Load_R1

=

0;Load_R2

=

0;Load_R3

=

0;Load_PC

=

0;Load_IR

=

0;Load_Add_R

=

0;Load_Reg_Y

=

0;Load_Reg_Z

=

0;Inc_PC

=

0;Sel_Bus_1

=

0;Sel_ALU

=

0;Sel_Mem

=

0;write

=

0;//

Used

for

de-bug

in

simulationerr_flag

=

0;next_state

=

state;case

(state)S_idle:S_fet1:S_fet2:next_state

=

S_fet1;beginnext_state

=

S_fet2;Sel_PC

=1;Sel_Bus_1

=

1;Load_Add_R=

1;endbeginnext_state

=

S_dec;Sel_Mem

=

1;Load_IR

=

1;Inc_PC

=

1;endRISC

CPU

设计实例case

(state)S_dec:case

(opcode)NOP: next_state

=

S_fet1;ADD,

SUB,

AND:

beginnext_state

=

S_ex1;

Sel_Bus_1

=

1;

Load_Reg_Y

=1;case

(src)Sel_R0

=

1;Sel_R1

=

1;Sel_R2

=

1;Sel_R3

=

1;err_flag

=

1;R0:R1:R2:R3:default

:endcaseend

//

ADD,

SUB,

ANDRISC

CPU

设计实例NOT:Sel_R0

=

1;Sel_R1

=

1;Sel_R2

=

1;Sel_R3

=

1;err_flag

=

1;beginnext_state

=

S_fet1;Load_Reg_Z

=

1;Sel_Bus_1

=

1;Sel_ALU

=

1;case

(src)R0:R1:R2:R3:default

:endcasecase

(dest)R0:R1:R2:R3:Load_R0

=

1;Load_R1

=

1;Load_R2

=

1;Load_R3

=

1;RD:default:

err_flag

=

1;endcaseend

//NOTbeginnext_state

=

S_rd1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//RDRISC

CPU

设计实例WR:BR:BRZ:beginnext_state

=

S_wr1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

WRbeginnext_state

=

S_br1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

BRif

(zero

==

1)

beginnext_state

=

S_br1;Sel_PC

=

1;

Sel_Bus_1

=

1;

Load_Add_R

=

1;end

//

BRZelse

beginnext_state

=

S_fet1;Inc_PC

=

1;endnext_state

=

S_halt;default

:endcase

//

(opcode)RISC

CPU

设计实例case

(state)S_ex1:S_rd1:S_wr1:beginnext_state

=

S_fet1;Load_Reg_Z

=

1;Sel_ALU

=

1;case

(dest)R0:

begin

Sel_R0

=

1;

Load_R0