基于fpgavga游戏俄罗斯方块

课程设计名 设计内容及要 系统设 系统框图与说 状态转换 输入输出设 输入设 输出设 测试平台设计 系统仿 课设总 附 square- 课程设计名称VGA俄罗斯方块设设计内容及要求系统设计GPIOGPIO换与消除模

3.1GPIO口与喇叭相连，俄罗斯民状态转换图3.2.1状编码方案说发如果反转信号3.2.2输入输出设计输入设计①第三组为Penter键，依次表示pausereset。②FPGAswitch0Reset输出设计①VGA②GPIO测试平台设计确，人对矩阵的敏感有限，不可能将一系列矩阵轻松地在脑海里转换成图像，所以该项设计故此，我直接使用了quartus系统仿真4.1波形仿真分析因为整个中VGA输出与键盘输入密切相关，所以事实上对与这两个模块相关的模块进行仿真意义不大，无法从PS2_DATA与VGA的输出中得到任何关于直观的感受，只能通过将课设总结心得体经历了漫长的四周，我终于完成了电子课设。在选题目的时候，，怀着自信念，我毫不豫的选择了VGA。但拿到题目之后，却发现这个学期是如此的繁忙，院篮球赛，GRE，课内学业，中途队伍又散了，只剩下我一个人完成这个本来由三个人完成的项目，这些东西都困扰着我，使得进度一开始的时候用sopc技术实现俄罗斯方块的设计，辛辛苦苦完成了SD卡读写文件和WAV文件的功能后，却被老师告知DE0板子资源有限，加载了sopc后就只能跑个跑马灯，那时我前俩周俄罗斯方块是大家耳熟能详的，小时候给带来了很多的欢乐，很多的愉悦，看起来只是几个一开始以为反转很容易，不就是一个原始矩阵乘上几个行列变换矩阵嘛，后来发现，Verilog待改进的问题功能拓附录moduleinputrst_n;

inputenable_red_border;input[9:0]count_v,count_h;inputenable_blue_moving;inputenable_blue_moving2;inputenable_green_score;output[3:0]Red,Green,Blue;wire[3:0]Red,Green,Blue;//wire//assignenable_blue=enable_blue_moving| wirereg[9:0]Xcoloradd;wire[3:0]colorR;wire[3:0]col;wire[3:0]colorB;wire[3:0]colorRR;wire[3:0]colG;wire[3:0]colorBB;assignen=1; if(!rst_n)Xcoloradd<=0; if(!rst_n)Ycoloradd<=0; ROMRGBrev_lenaRu4(coloradd,clk_25M,colorRR);rev_lenaGu5(coloradd,clk_25M,colG);rev_lenaBu6(coloradd,clk_25M,colorBB); wire

//outputtwo Blue[3]=(valid&&en&&enb)?1:(valid&&!SW)?colorBB[3]:0; Blue[2]=(valid&&en&&enb)?1:(valid&&!SW)?colorBB[2]:0; Blue[1]=(valid&&en&&enb)?1:(valid&&!SW)?colorBB[1]:0; Blue[0]=(valid&&en&&enb)?1:(valid&&!SW)?colorBB[0]:0; Green[3]=(valid&&en&&eng)?1:(valid&&!SW)?colG[3]:0; Green[2]=(valid&&en&&eng)?1:(valid&&!SW)?colG[2]:0; Green[1]=(valid&&en&&eng)?1:(valid&&!SW)?colG[1]:0; Green[0]=(valid&&en&&eng)?1:(valid&&!SW)?colG[0]:0; Red[3]= Red[2]= Red[1]= square-moduleinputinputrotate_R;inputloading_square;input[223:0]enable_little;inputbeginh;reg[15:0]enable_moving;regrotate_R_dly;wirerotate_en;//******Updatathevalueofenable_movingtodisplaythefallingalways@(posedgeclk_25Mornegedgerst_n)elseif(loading_square)

3'b000:enable_moving<=16'b0000_0000_0011_0011;//0o3'b001:enable_moving<=16'b0000_0000_0111_0010;//1T3'b010:enable_moving<=16'b0010_0010_0010_0010;//2l3'b011:enable_moving<=16'b0000_0000_0011_0110;//3zenable_moving[0]<=enable_moving_rotate[0];enable_moving[1]<=enable_moving_rotate[1];enable_moving[2]<=enable_moving_rotate[2];enable_moving[4]<=enable_moving_rotate[4];enable_moving[5]<=enable_moving_rotate[5];enable_moving[6]<=enable_moving_rotate[6];enable_moving[7]<=enable_moving_rotate[7];enable_moving[8]<=enable_moving_rotate[8];enable_moving[9]<=enable_moving_rotate[9];enable_moving[11]<=enable_moving_rotate[11];enable_moving[13]<=enable_moving_rotate[13];enable_moving[14]<=enable_moving_rotate[14]; //Changethetypeofthereg[2:0]sh always@(posedgeclk_25Mornegedgerst_n)else <=shsquare_type<= square_type<=//Determiniftheunitcanbe always@(posedgeclk_25Mornegedgerst_n)elseif(ready)enable_moving_rotate[1]<=enable_moving[8];enable_moving_rotate[2]<=enable_moving[4];enable_moving_rotate[7]<=enable_moving[1];enable_moving_rotate[11]<=enable_moving[2]; <=enable_moving[13];enable_moving_rotate[8]<=enable_moving[14]; enable_moving_rotate[10]<=enable_moving[6];

<=enable_moving[8]; <=enable_moving[4]; <=enable_moving[0]; <=enable_moving[1]; <=enable_moving[6]; enable_moving_rotate[4]<=enable_moving[9]; else

<= <= <= <= assignrotate_en=!((enable_moving_rotate[0]&&enable_little[little_square_num])|| &&enable_little[little_square_num+1'd1])|| &&enable_little[little_square_num+2'd2])|| &&enable_little[little_square_num+2'd3])|| &&enable_little[little_square_num+5'd14])|| &&enable_little[little_square_num+5'd15])|| &&enable_little[little_square_num+5'd16])|| &&enable_little[little_square_num+5'd17])|| &&enable_little[little_square_num+6'd28])|| &&enable_little[little_square_num+6'd29])||(enable_moving_rotate[10]&&enable_little[little_square_num+6'd30])||(enable_moving_rotate[11]&&enable_little[little_square_num+6'd31])||(enable_moving_rotate[12]&&enable_little[little_square_num+6'd42])||(enable_moving_rotate[13]&&enable_little[little_square_num+6'd43])||(enable_moving_rotate[14]&&enable_little[little_square_num+6'd44])||(enable_moving_rotate[15]&&enable_little[little_square_num+6'd45]));

rotate_R_dly<=rotate_R_dly<=moduleinputclk;

inputPS2_CLK_Pin_In;outputhsync,vsync;outputbeep;wirehsync,vsync;wireclk_50M;wireclk_25M;wirerst_n;wire[9:0]count_h;wire[9:0]count_v;wiremove_right;wiremove_left;wirerotate_R;wiremove_down;wiremove_left_a;wirerotate_R_w;wirepause;wirewirewirewiresub_line_total;wireenable_red_border;wireenable_blue_moving;wireenable_green_score;wire[223:0]enable_little;wire[15:0]enable_moving;wireupdown;wire[2:0]sumsub;wire[9:0]h2;wirewirewireenable_blue_moving2;wire[15:0]enable_moving2;wireready;wirewireenable_green_english;assignrst_n=rst_n1&&(!restart);pll//themoduleclk_ctlfuncu_func(en_littleassign

biu

moduleinputrst_n;inputbigend;outputenable_blue_little_flag;regenable_blue_little_flag;reg[223:0]

wireenable_blue_little_flag_tmp1;wire[223:0]enable_blue_little;outputupdown;reg[7:0]elsemoduleinputrst_n;inputupdown;inputbigbang;inputinput[9:0]count_h,count_v;input[15:0]enable_moving; parametersquare_width=5'd16;wireenable_moving_temp;reg[6:0]x;integery;

always@(posedgeclk_25Mornegedgerst_n) enable_blue_moving<=1'b0;

if(x[3:0]!=0&&y[3:0]!=0) elseenable_blue_moving<=0;moduleinputrst_n;input

regenable_red_border;regenable_red_out_h;///Theparametersarethegame's ///Displaytheoutenable_red_out_h<= enable_red_out_h<= enable_red_out_h<=enable_red_out_h<=enable_red_out_v<= enable_red_out_v<= enable_red_out_v<=enable_red_out_v<=///Displaytheinsideenable_red_in_h<= enable_red_in_h<=

enable_red_in_h<=1'b0;enable_red_in_v<= enable_red_in_v<= enable_red_in_v<=enable_red_in_v<=assignenable_red_border_tmp=(enable_red_out_v&&enable_red_out_h)&&(!(enable_red_in_h&&enable_red_border<=enable_red_border<=moduleinputinputinputinput[2:0]sumsub;inputregenable_green_score;reg[3:0]h;reg[199:0]number_tag;parameterv_startelsebegin1:beginif(shi>9)beginbai=bai+1;shi=shi-10;endif(bai>9)beginqian=qian+1;bai=bai-10;endif(qian>9)beginqian=0;bai=0;shi=0;ge=0;end2:beginif(ge>9)beginshi=shi+1;ge=ge-10;endif(shi>9)beginbai=bai+1;shi=shi-10;endif(bai>9)beginqian=qian+1;bai=bai-10;endif(qian>9)beginqian=0;bai=0;shi=0;ge=0;end3:beginif(shi>9)beginbai=bai+1;shi=shi-10;endif(bai>9)beginqian=qian+1;bai=bai-10;endif(qian>9)beginqian=0;bai=0;shi=0;ge=0;end4:beginif(ge>9)beginshi=shi+1;ge=ge-10;endif(shi>9)beginbai=bai+1;shi=shi-10;endif(bai>9)beginqian=qian+1;bai=bai-10;endif(qian>9)beginqian=0;bai=0;shi=0;ge=0;end

default:beginge=ge;shi=shi;bai=bai;qian=qian;end

moduleinputrst_n;inputoutputreg[9:0]h;regparameterv_start

elsemoduleinputrst_n;inputoutputreg[9:0]h;regparameterv_start

else`timescale1ns/inputclk_25M,rst_n;inputkey_in;wireregkey_out_tmp;reg[20:0]

key_out_tmp<=1'b0;

assignkey_out=key_out_tmp&moduleinputrst_n;inputPS2_Done_Sig;input[7:0]PS2_Data;outputmove_right_d;outputmove_left_a;outputrotate_R_w;

if(rData==4'b1000)if(rData==4'b0100)if(rData==4'b0010)if(rData==4'b0001)elseassignmove_left_a=rData[2];assignrotate_R_w=rData[3];moduleinputrst_n;outputmove_right;outputmove_left;outputrotate_R;outputpause;outputrestart;reg[5:0]rData;regen_pause;if(rData==6'b000100)if(rData==6'b000010)if(rData==6'b001000)if(rData==6'b000001)if(rData==6'b010000)if(rData==6'b100000)elseassignmove_right=rData[0];assignmove_left=rData[1];assignrotate_R=rData[2];assignpause=rData[4];assignrestart=rData[5];moduleinputrst_n;outputclk_25M;outputhsync;outputvsync;reghsync; if

clk_25M<=//----------countthehlinesandv always@(posedgeclk_25Mornegedgerst_n)if(!rst_ncount_v<=elseif(count_h==10'd799)if(count_v==10'd520)

count_v<=count_v+

count_h<=count_h+ always@(posedgeclk_25Mornegedgerst_n)if(!rst_nvsync<=

moduleinputrst_n;

outputbeep;reg[5:0]state;reg[14:0]count;reg[22:0]count1;regen; L_6=L_7=M_1=M_2=M_3=M_4=M_5=M_6= =parameterTIME=23'd400_0000;assignbeep=*controlfreqofalways@(posedgeclk_25Mornegedgerst_n)count<=count+1'b1;count<=15'h0;beep_r<=count<=count+1'b1;count<=15'h0;

**controltimeofsound---always@(posedgeclk_25Mornegedgerst_n)state=if(count1<count1=count1+if(state==63)

state=state=state+

default:count_end=15'h0;always@(posedgeclk_25Mornegedgerst_n)elsebeginif(count2<TIME_biu)count2=23'd0;state_biu=0;

default:count_end_biu=15'h0;moduleinputrst_n;outputready;regready;inputdead;inputbigbang;inputpause;regpau;begin//megafunctionwizard:%ROM:1-//VERSION://MODULE:////FileName://Megafunction //SimulationLibrary //////THISISAWIZARD-GENERATEDFILE.DONOTEDITTHIS//9.0Build13202/25/2009SJFull////Copyright(C)1991-2009Altera//YouruseofAlteraCorporation'sdesigntools,logic//andothersoftwareandtools,anditsAMPPpartner//functions,andanyoutputfilesfromanyofthe//(includingdeviceprogrammingorsimulationfiles),and//associatedationorinformationareexpressly//tothetermsandconditionsoftheAlteraProgram//Agreement,orotherapplicablelicenseagreement,//withoutlimitation,thatyouruseisforthesolepurpose//programminglogicdevicesmanufacturedbyAlteraandsold//Alteraoritsauthorized Pleasereferto//applicableagreementforfurther//synopsys`timescale1ps/1modulelenaB( wire[3:0]wire[3:0]q= ponent.clock0.q_a.aclr0.aclr1.byteena_a.clock1.data_a.q_b.rden_a

ponent.address_aclr_a="NONE",ponent.clock_enable_input_a="BYPASS",ponent.clock_enable_output_a="BYPASS",ponent.init_file="../lena__mif/lenaB.mif",ended_device_family="CycloneIII",ponent.lpm_hint="ENABLE_RUNTIME_MOD=NO",ponent.lpm_type="altsyncram",ponent.numwords_a=16384,ponent.operation_mode="ROM",ponent.outdata_aclr_a="NONE",ponent.widthad_a=14,ponent.width_a=////CNXfileretrieval////Retrievalinfo:PRIVATE:AclrAddrNUMERIC//Retrievalinfo:PRIVATE:AclrByte//Retrievalinfo:PRIVATE:AclrOutputNUMERIC//Retrievalinfo:PRIVATE:BYTE_ENABLE//Retrievalinfo:PRIVATE:BYTE_SIZE//Retrievalinfo:PRIVATE:BlankMemoryNUMERIC//Retrievalinfo:PRIVATE:CLOCK_ENABLE_OUTPUT_ANUMERIC//Retrievalinfo:PRIVATE:ClkenNUMERIC//Retrievalinfo:PRIVATE:IMPLEMENT_IN_LESNUMERIC//Retrievalinfo:PRIVATE:INIT_TO_SIM_XNUMERIC//Retrievalinfo:PRIVATE:UM_DEPTHNUMERIC//Retrievalinfo:PRIVATE:NUMWORDS_A//Retrievalinfo:PRIVATE:RAM_BLOCK_TYPENUMERIC//Retrievalinfo:PRIVATE:RegAddrNUMERIC//Retrievalinfo:PRIVATE:RegOutputNUMERIC//Retrievalinfo:PRIVATE:SingleClockNUMERIC//Retrievalinfo:PRIVATE:UseDQRAMNUMERIC//Retrievalinfo:PRIVATE:WidthAddrNUMERIC//Retrievalinfo:PRIVATE:WidthData//Retrievalinfo:PRIVATE:rdenNUMERIC//Retrievalinfo:CONSTANT:ADDRESS_ACLR_ASTRING//Retrievalinfo:CONSTANT:NUMWORDS_ANUMERIC//Retrievalinfo:CONSTANT:WIDTHAD_A//Retrievalinfo:CONSTANT:WIDTH_A//Retrievalinfo:CONSTANT:WIDTH_BYTEENA_A//Retrievalinfo:USED_PORT:address00140INPUTNODEFVAL//Retrievalinfo:USED_PORT:clock0000INPUTNODEFVAL//Retrievalinfo:USED_PORT:q0040OUTPUTNODEFVAL//Retrievalinfo:CONNECT:@address_a00140address0014//Retrievalinfo:CONNECT:q0040@q_a004//Retrievalinfo:CONNECT:@clock00000clock000//Retrievalinfo:LIBRARY:altera_mf //Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB.inc//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB.cmp//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaf//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB_inst.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB_bb.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB_waveforms.html//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaB_wave*.jpg//Retrievalinfo:LIB_FILE://megafunctionwizard:%ROM:1-//VERSION://MODULE:////FileName://Megafunction //SimulationLibrary //////THISISAWIZARD-GENERATEDFILE.DONOTEDITTHIS//9.0Build13202/25/2009SJFull////Copyright(C)1991-2009Altera//YouruseofAlteraCorporation'sdesigntools,logic//andothersoftwareandtools,anditsAMPPpartner//functions,andanyoutputfilesfromanyofthe//(includingdeviceprogrammingorsimulationfiles),and//associatedationorinformationareexpressly//tothetermsandconditionsoftheAlteraProgram//Agreement,orotherapplicablelicenseagreement,//withoutlimitation,thatyouruseisforthesolepurpose//programminglogicdevicesmanufacturedbyAlteraandsold//Alteraoritsauthorized Pleasereferto//applicableagreementforfurther//synopsys`timescale1ps/1modulelenaG( wire[3:0]wire[3:0]q= ponent.clock0.q_a.aclr0

.aclr1.byteena_a.clock1.data_a.q_b.rden_aponent.address_aclr_a="NONE",ponent.clock_enable_input_a="BYPASS",ponent.clock_enable_output_a="BYPASS",ponent.init_file="../lena__mif/lenaG.mif",ended_device_family="CycloneIII",ponent.lpm_hint="ENABLE_RUNTIME_MOD=NO",ponent.lpm_type="altsyncram",ponent.numwords_a=16384,ponent.operation_mode="ROM",ponent.outdata_aclr_a="NONE",ponent.outdata_reg_a="CLOCK0",ponent.widthad_a=14,ponent.width_a=////CNXfileretrieval////Retrievalinfo:PRIVATE:AclrAddrNUMERIC//Retrievalinfo:PRIVATE:AclrByte//Retrievalinfo:PRIVATE:AclrOutputNUMERIC//Retrievalinfo:PRIVATE:BYTE_ENABLE//Retrievalinfo:PRIVATE:BYTE_SIZE//Retrievalinfo:PRIVATE:BlankMemoryNUMERIC//Retrievalinfo:PRIVATE:CLOCK_ENABLE_OUTPUT_ANUMERIC//Retrievalinfo:PRIVATE:ClkenNUMERIC//Retrievalinfo:PRIVATE:IMPLEMENT_IN_LESNUMERIC//Retrievalinfo:PRIVATE:INIT_TO_SIM_XNUMERIC//Retrievalinfo:PRIVATE:UM_DEPTHNUMERIC//Retrievalinfo:PRIVATE:NUMWORDS_A//Retrievalinfo:PRIVATE:RAM_BLOCK_TYPENUMERIC//Retrievalinfo:PRIVATE:RegAddrNUMERIC//Retrievalinfo:PRIVATE:RegOutputNUMERIC//Retrievalinfo:PRIVATE:SingleClockNUMERIC//Retrievalinfo:PRIVATE:UseDQRAMNUMERIC//Retrievalinfo:PRIVATE:WidthAddrNUMERIC//Retrievalinfo:PRIVATE:WidthData//Retrievalinfo:PRIVATE:rden//Retrievalinfo:CONSTANT:ADDRESS_ACLR_ASTRING//Retrievalinfo:CONSTANT:NUMWORDS_ANUMERIC//Retrievalinfo:CONSTANT:WIDTHAD_A//Retrievalinfo:CONSTANT:WIDTH_A//Retrievalinfo:CONSTANT:WIDTH_BYTEENA_A//Retrievalinfo:USED_PORT:address00140INPUTNODEFVAL//Retrievalinfo:USED_PORT:clock0000INPUTNODEFVAL//Retrievalinfo:USED_PORT:q0040OUTPUTNODEFVAL//Retrievalinfo:CONNECT:@address_a00140address0014//Retrievalinfo:CONNECT:q0040@q_a004//Retrievalinfo:CONNECT:@clock00000clock000//Retrievalinfo:LIBRARY:altera_mf //Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG.inc//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG.cmp//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG.bsf//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG_inst.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG_bb.v//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG_waveforms.html//Retrievalinfo:GEN_FILE:TYPE_NORMALlenaG_wave*.jpg//Retrievalinfo:LIB_FILE://megafunctionwizard:%ROM:1-//VERSION://MODULE:////FileName://Megafunction //SimulationLibrary //////THISISAWIZARD-GENERATEDFILE.DONOTEDITTHIS//9.0Build13202/25/2009SJFull////Copyright(C)1991-2009Altera//YouruseofAlteraCorporation'sdesigntools,logic//andothersoftwareandtools,anditsAMPPpartner//functions,andanyoutputfilesfromanyofthe//(includingdeviceprogrammingorsimulationfiles),and//associatedationorinformationareexpressly//tothetermsandconditionsoftheAlteraProgram//Agreement,orotherapplicablelicenseagreement,//withoutlimitation,thatyouruseisforthesolepurpose//programminglogicdevicesmanufacturedbyAlteraandsold//Alteraoritsauthorized Pleasereferto//applicableagreementforfurther//synopsys`timescale1ps/1modulelenaR( wire[3:0]wire[3:0]q= ponent.clock0.q_a.aclr0.aclr1.byteena_a.clock1.data_a.q_b.rden_a

ponent.address_aclr_a="NONE",ponent.c