电子竞赛优秀获奖简易逻辑分析仪设计报告

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6、rucharj-j+1-%16voiderruptvoiderrupterruptuchar%17 errupt%18void main(void)erruptvoid main(void)errupterrupt%19%JVHDLlibrary%JVHDLlibraryuseuseieee.std_logic_unsigned.all; entity rd isrd:inrami:instd_logic_vector(7downto0); cs,we,oe,tong:out std_logic; endarchitecturerd_arcofrdis variableabc:std_logi

7、c_vector(7downto0); variable seger range 0 to 499;rd=0 %20elsifclk4Meventandclk4M=1then case se iswhenelsifclk4Meventandclk4M=1then case se iswhenwhenwhenwhen 499=swhen others=sendif abc19 then endifpdata=1ifabc=00000000then end if;ifabc=00001010then end if;endend if; end proend%21libraryuseuseieee.std_logic_unsigned.all; entity counter8 is libraryuseuseieee.std_logic_unsigned.all; entity counter8 is q:outstd_logic_vector(2downto0); end counter8;architect