EDA流水灯底层文件代码教案资料

1、Good is good, but better carries it.精益求精，善益求善。EDA流水灯底层文件代码-libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitydivisPORT(CLK_IN:INSTD_LOGIC;-输入时钟信号CLK_OUT:OUTSTD_LOGIC-分频后的输出时钟信号);enddiv;architectureBehavioralofdivissignalcont:STD_logic_vector(1dow

2、nto0);beginprocess(CLK_IN)BEGINIFRISING_EDGE(CLK_IN)THENIFCONT=11THENCONT=00;CLK_OUT=1;ELSECONT=CONT+1;CLK_OUT=0;ENDIF;ENDIF;ENDPROCESS;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityled0isPORT(CLK:INSTD_LOGIC;-分频后的时钟信号EN:INSTD_L

3、OGIC;-使能控制信号M:OUTSTD_LOGIC_VECTOR(7DOWNTO0)-控制8个灯的输出信号);endled0;architectureBehavioralofled0isSIGNALSEL:STD_LOGIC_VECTOR(2DOWNTO0);beginPROCESS(EN,CLK,SEL)BEGINIFRISING_EDGE(CLK)THENIFEN=1THENIFSEL=111THENSEL=000;ELSESELMMMMMMMMNULL;ENDCASE;ENDPROCESS;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164

4、.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityled1isPORT(CLK:INSTD_LOGIC;-分频后的时钟信号EN:INSTD_LOGIC;-使能控制信号N:OUTSTD_LOGIC_VECTOR(7DOWNTO0)-控制8个灯的输出信号);endled1;architectureBehavioralofled1isSIGNALSEL:STD_LOGIC_VECTOR(2DOWNTO0);beginPROCESS(EN,CLK,SEL)BEGINIFRISING_EDGE(CLK)THENIF

5、EN=1THENIFSEL=111THENSEL=000;ELSESELNNNNNNNNNULL;ENDCASE;ENDPROCESS;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityled2isPORT(CLK:INSTD_LOGIC;-分频后的时钟信号EN:INSTD_LOGIC;-使能控制信号L:OUTSTD_LOGIC_VECTOR(7DOWNTO0)-控制8个灯的输出信号);endled2;arch

6、itectureBehavioralofled2isSIGNALSEL:STD_LOGIC_VECTOR(2DOWNTO0);beginPROCESS(EN,CLK,SEL)BEGINIFRISING_EDGE(CLK)THENIFEN=1THENIFSEL=111THENSEL=000;ELSESELLLLLLLLLNULL;ENDCASE;ENDPROCESS;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;enti

7、tyled3isPORT(CLK:INSTD_LOGIC;-分频后的时钟信号EN:INSTD_LOGIC;-使能控制信号Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0)-控制8个灯的输出信号);endled3;architectureBehavioralofled3isSIGNALSEL:STD_LOGIC_VECTOR(2DOWNTO0);beginPROCESS(EN,CLK,SEL)BEGINIFRISING_EDGE(CLK)THENIFEN=1THENIFSEL=111THENSEL=000;ELSESELQQQQQQQQNULL;ENDCASE;ENDPROCESS;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitymux41isPORT(a,b,c,d:INSTD_LOGIC;din:INSTD_LOGIC_vector(1downto0);dout:OUTSTD_LOGIC);endmux41;architectureBehavioralofmux41issignalsel:STD_