数字IC后端流程

1、2020/7/23,1,cmos集成电路版图,-概念、方法与工具,第6ic,2020/7/23,2,数字ic后端流程,placement,design planning,cts,route,dfm & chip finishing,data setup,2020/7/23,3,基于icc的数字ic后端设计流程,use ic compiler to perform placement, dft, cts, routing and optimization, achieving timing closure for designs with moderate to hi

2、gh design challenges.,2020/7/23,4,基于icc的数字ic后端设计流程,there is no “golden script” for physical design,2020/7/23,5,data setup,布局布线的准备工作，读入网表，跟foundry提供的std cell、 pad库以及macro库进行映射。,2020/7/23,6,data setup,后端设计数据准备 设计网表 gate-level netlist 设计约束文件 sdc file 物理库文件 sc.lef/io.lef/macro.lef 时序库文件 sc.lib/io.lib/ma

3、cro.lib i/o文件 i/o constraints file（.tdf） 工艺文件 technology file（.tf） rc模型文件 tlu+,2020/7/23,7,data setup,logical libraries provide timing and functionality information for all standard cells (and, or, flipflop, ) provide timing information for hard macros (ip, rom, ram, ) define drive/load design rules

4、: max fanout max transition max/min capacitance are usually the same ones used by design compiler during synthesis are specified with variables: target_library link_library,2020/7/23,8,data setup,逻辑单元库：一个完整的单元库由不同的功能电路所组成，种类和数量很多，根据其应用可分为三类： 标准单元（standard cells） 组合逻辑 时序逻辑 模块宏单元（macro block） rom ram

5、专用模块（如assp、dsp等） black box商业ip（如arm、标准单元等） 模拟模块（如pll、振荡器等） 输入输出单元（i/o pad cell） 输入 输出 三态 双向,考虑esd,2020/7/23,9,data setup,physical reference libraries,2020/7/23,10,data setup,物理单元库：和逻辑单元库分类相同，但也包括一些特殊单元，在后端物理实现中的作用有别于其他逻辑电路 填充单元（filler/spacer） i/o spacer用于填充i/o单元之间的空隙以形成power ring 标准单元filler cell与逻辑无

6、关，用于把扩散层连接起来满足drc规则和设计需求，并形成power rails 电压钳位单元（tie-high/tie-low） 二极管单元（diode），对违反天线规则的栅输入端加入反偏二极管，避免天线效应将栅氧击穿 时钟缓冲单元（clock buffer/clock inverter）：为最小化时钟偏差（skew），插入时钟缓冲单元来减小负载和平衡延时 延时缓冲单元（delay buffer）：用于调节时序 阱连接单元（well-tap cell）：主要用于限制电源或地与衬底之间的 电阻大小，减小latch-up效应 电压转换单元（level-shifter）：多用于低功耗设计,2020/

7、7/23,11,data setup,库文件 时序库：描述单元库中各个单元时序信息的文件。（.lib库） 单元延时 互连线延时 物理库：是对版图的抽象描述，她使自动布局布线成为可能且提高了工具效率（.lef库），包含两部分 技术lef：定义布局布线的设计规则和foundry的工艺信息 单元lef：定义sc、macro、i/o和各种特殊单元的物理信息，如对称性、面积大小、布线层、不可布线区域、天线效应参数等,2020/7/23,12,data setup,the technology file (.tf file)：the technology file is unique to each te

8、chnology；contains metal layer technology parameters: number and name designations for each layer/via physical and electrical characteristics of each layer/via design rules for each layer/via (minimum wire widths and wire-to-wire spacing, etc.) units and precision for electrical units colors and patt

9、erns of layers for display ,2020/7/23,13,1. specify the logical libraries,2020/7/23,14,2. define logic0 and logic1,2020/7/23,15,3. create a “container”: the design library,2020/7/23,16,4. specify tlu+ parasitic rc model files,tlu+ is a binary table format that stores the rc coefficients,2020/7/23,17

10、,timing is based on cell and net delays,2020/7/23,18,5. create design cel,2020/7/23,19,6. verify logical libraries are loaded,2020/7/23,20,7. define logical power/ground connections,2020/7/23,21,8. apply and check timing constraints,2020/7/23,22,9. remove unwanted “ideal net/networks”,2020/7/23,23,1

11、0. save the design,its good practice to save the design after each key design phase, for example: data setup, design planning, placement, cts and routing: note: the open cell is still the original orca cell !,save_mw_cel as orca_data_setup,2020/7/23,24,数字ic后端流程,placement,design planning,cts,route,df

12、m & chip finishing,data setup,2020/7/23,25,design planning,芯片设计的物理实施通常被简称为布局布线（p&r，place-and-route），而p&r之前的大量工作，包括data setup、floor-plan、power-plan亦非常关键。,布图规划的主要内容包括芯片大小（die size）的规划、i/o规划、大量硬核或模块（hard core、block）的规划等，是对芯片内部结构的完整规划和设计。,布图规划的合理与否直接关系到芯片的时序收敛、布线通畅（timing and routability）。,create a floo

13、rplan that is likely to be routable and achieve timing closure,2020/7/23,26,icc terminology,design planning is the iterative process of creating a floorplan。,a chip-level floorplan entails defining: core size, shape and placement rows periphery: io, power, corner and filler pad cell locations macro

14、cell placement power grid (rings, straps, rails),a physical design, or layout, is the result of a synthesized netlist that has been placed and routed,2020/7/23,27,create physical-only pad cells,physical-only pad cells (vdd/gnd, corner cells) are not part of the synthesized netlist must be created pr

15、ior to specifying the pad cell locations,open_mw_cel design_data_setup create_cell vss_l vss_r vss_t vss_b pv0i create_cell vdd_l vdd_r vdd_t vdd_b pvdi create_cell cornerll cornerlr cornertr cornertl pfrelr,2020/7/23,28,specify pad cell locations,2020/7/23,29,initialize the floorplan,2020/7/23,30,c

16、ore area parameters,2020/7/23,31,floorplan after initialization,2020/7/23,32,insert pad filler cells,insert_pad_filler cell “fill5000 fill2000 fill1000 . ,2020/7/23,33,constraining macros：manually,2020/7/23,34,macro constraints: anchor bound option,2020/7/23,35,macro constraints: side channel option

17、,side channels are regions along the core edges where placement of macros is not allowed.,set_fp_macro_array name array_a elements get_cells “a1 a2 a3” set_fp_macro_options array_a side_channel “0 80 30 40”,2020/7/23,36,电源规划,电源规划是给整个芯片的供电设计出一个均匀的网络。,电源预算（power budgeting），商用惯例为误差在5%，包括 从电源网络和pcb板级到封装

18、bonding之间的波动（1%） 电源i/o单元和电源环之间的波动（1%） 最终到sc之间的电压降（3%）,2020/7/23,37,电源网络设计,全局电源,电源环线（power ring）指为了均匀供电，包围在sc周围的环形供电金属，用于连接电源i/o单元和sc的followingpins,电源条线（power strips）指芯片内部纵横交错的电源网格（power grid）,2020/7/23,38,power plan,2020/7/23,39,write out floorplan and def files,设计交换格式def（design exchange format）文件是由

19、cadence公司开发的用于描述文件物理设计信息的一种文件格式。,def描述了芯片的die area、row、tracks、components、nets等,对于设计者而言，有了lef和def文件就可以完整的了解一个设计,2020/7/23,40,数字ic后端流程,placement,design planning,cts,route,dfm & chip finishing,data setup,2020/7/23,41,placement,布局的主要任务是sc的摆放和优化,布局算法一直是eda设计中的研究重点，目前仍在发展。,in most situations macro cell pl

20、acement is determined during design planning and their placement is “fixed” it is a good practice to fix all macro placements again, just in case.,2020/7/23,42,placement,2020/7/23,43,数字ic后端流程,placement,design planning,cts,route,data setup,2020/7/23,44,芯片中的时钟网络要驱动电路中所有的时序单元，所以时钟负载延时很大并且不平衡，需要插入缓冲器减小负载和平衡延时。 时钟网络及其上的缓冲器构成了时钟树。 cts的目的是为了减小时钟偏差（clock skew） 时钟信号定义 sdc cts策略 时钟树分析,clock tree synthesis,2020/7/23,45,starting poi