集成电路设计-05-反相器动静态特性

集成电路设计第五章CMOS反相器1EIS-WUHANUNIVERSITYOutline电路特性反相器CMOS反相器电压传输特性噪声容限传输延迟驱动大电容负载功耗及低功耗设计2EIS-WUHANUNIVERSITY5-1特性成本复杂性和面积完整性和稳定性静态（稳态）特性性能动态（瞬态）特性能量效率能耗和功率3EIS-WUHANUNIVERSITY5-2反相器（Inverter）VinVoutCLVDDCMOSInverterPolysiliconInOutVDDGNDPMOS2lMetal1NMOSContactsNWell4EIS-WUHANUNIVERSITYTwoInvertersConnectinMetalSharepowerandground5EIS-WUHANUNIVERSITYCMOS反相器基本特点输出电源和GND噪声容限大逻辑电平与尺寸无关，可以采用最小尺寸稳态输出时，VDD或GND与输出之间总存在有限电阻的通路低输出阻抗对噪声和干扰不敏感极高的输入阻抗（inputresistance）稳态下Vdd

和GND间无直流通路无静态功耗传输延迟（Propagationdelay）是负载电容和晶体管电阻的函数。6EIS-WUHANUNIVERSITYCMOSInverter

——First-OrderDCAnalysisVOL=0VOH=VDDVM=f(Rn,Rp)VDDVDDVin=VDDVin=0VoutVoutRnRp7EIS-WUHANUNIVERSITYCMOSInverter:TransientResponse

tpHL

=f(Ron.CL)=0.69RonCLVoutVoutRnRpVDDVDDVin=VDDVin=0(a)Low-to-high(b)High-to-lowCLCL8EIS-WUHANUNIVERSITY5-3VoltageTransferCharacteristicNMOS+PMOS图解法9EIS-WUHANUNIVERSITYI-VNMOSID(A)VDS(V)X10-4VGS=1.0VVGS=1.5VVGS=2.0VVGS=2.5VLineardependenceNMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=0.4V10EIS-WUHANUNIVERSITYI-VPlot(PMOS)ID(A)VDS(V)X10-4VGS=-1.0VVGS=-1.5VVGS=-2.0VVGS=-2.5VPMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=-0.4VAllpolaritiesofallvoltagesandcurrentsarereversed11EIS-WUHANUNIVERSITYPMOSLoadLinesVoutIDnVin=VDD+VGSpIDn=-IDpVout=VDD+VDSpVinVoutCLVDD12EIS-WUHANUNIVERSITYPMOSLoadLinesVDSpIDpVGSp=-2.5VGSp=-1VDSpIDnVin=0Vin=1.5VoutIDnVin=0Vin=1.5Vin=VDD+VGSpIDn=-IDpVout=VDD+VDSp13EIS-WUHANUNIVERSITYCMOSInverterLoadCharacteristics

14EIS-WUHANUNIVERSITYCMOSInverterVTC

15EIS-WUHANUNIVERSITY噪声容限logic1logic0unknownVDDVSSVHVL反映了对噪声的敏感程度；电路0，1电平允许的输入范围；越大越好；高电平噪声容限低电平噪声容限16EIS-WUHANUNIVERSITYLogiclevelmatchingLevelsatoutputofonegatemustbesufficienttodrivenextgate.17EIS-WUHANUNIVERSITYTransfercharacteristicsTransfercurveshowsstaticinput/outputrelationship—holdinputvoltage,measureoutputvoltage.18EIS-WUHANUNIVERSITY反相器噪声容限的三种求法求法1最低输出高电平、最高输出低电平；找到对应的输入；求差；VNL=Voff–VilVNH=Vih–VonVolVol,maxVoh,minVohVonVihVoffVil19EIS-WUHANUNIVERSITY求法2单位增益点（斜率为1，-1）；找到对应的输入；求差；VNL=Voff–VilVNH=Vih–VonVolVol,maxVoh,minVohVonVihVoffVil20EIS-WUHANUNIVERSITY求法3工作中心点；Vin=VoutVgs=Vds找到对应的输入；求差；21EIS-WUHANUNIVERSITYNoiseMarginsDeterminingVIHandVILVinVoutVOH=VDDVMBydefinition,VIHandVILarewheredVout/dVin=-1(=gain)VOL=GNDApiece-wiselinearapproximationofVTCNMH=VDD-VIHNML=VIL-GNDApproximating:VIH=VM-VM/gVIL=VM+(VDD-VM)/gSohighgaininthetransitionregionisverydesirable22EIS-WUHANUNIVERSITYCMOSInverterVTCfromSimulationVin(V)Vout(V)0.25um,(W/L)p/(W/L)n=3.4(W/L)n=1.5(minsize)VDD=2.5VVM

1.25V,g=-27.5VIL=1.2V,VIH=1.3VNML=NMH=1.2(actualvaluesareVIL=1.03V,VIH=1.45VNML=1.03V&NMH=1.05V)Outputresistancelow-output=2.4k

high-output=3.3k

23EIS-WUHANUNIVERSITYVM与PMOS及NMOS的宽长比(W/L)p/(W/L)nVM(V)IncreasingthewidthofthePMOSmovesVMtowardsVDDIncreasingthewidthoftheNMOSmovesVMtowardGND决定因素：宽长比近似为等效电阻之比。.1工艺因子：k’=µCox导电因子：βn

=k’（W/L）~3.4Rn≈1/[βn

(Vgs–Vt)]24EIS-WUHANUNIVERSITYGainDeterminatesVingainGainisastrongfunctionoftheslopesofthecurrentsinthesaturationregion,forVin=VM(1+r)g

----------------------------------(VM-VTn-VDSATn/2)(

n-

p)Determinedbytechnologyparameters,especiallychannellengthmodulation().OnlydesignerinfluencethroughsupplyvoltageandVM(transistorsizing).25EIS-WUHANUNIVERSITYGainasafunctionofVDDGain=-1100mv时，VTC变差；过渡区增益接近-1一般，为达到足够的增益，电源应大于热电势的两倍VDDmin>2,4KT/qKT/q室温下约为26mv26EIS-WUHANUNIVERSITYSimulatedVTC

27EIS-WUHANUNIVERSITYImpactofProcessVariations00.511.522.500.511.522.5Vin(V)Vout(V)GoodPMOSBadNMOSGoodNMOSBadPMOSNominal28EIS-WUHANUNIVERSITY5-4传输延迟（PropagationDelay）29EIS-WUHANUNIVERSITYDelayAssumeidealinput(step),RCload.30EIS-WUHANUNIVERSITYtpHL

=f(Ron.CL)=0.69RonCLVoutVoutRnRpVDDVDD(a)Low-to-high(b)High-to-lowCLCL上升时间（risetime）,pullupon;下降时间（falltime）,pullupoff.31EIS-WUHANUNIVERSITYCurrentthroughtransistorTransistorstartsinsaturationregion,thenmovestolinearregion.Vout增大充电电流减小。

Vds

减小。32EIS-WUHANUNIVERSITYResistiveapproximation可使用积分求解等效电阻平均值33EIS-WUHANUNIVERSITYReq

——求VDD/2，VDD区间的电阻平均值34EIS-WUHANUNIVERSITYGatedelayDelay:

传输延迟VDD

50%VDD50%VDD

VDDTransitiontime:

转换时间timerequiredforgate’soutputtoreach10%(logic0)or90%(logic1)offinalvalue.10%

90%90%

10%35EIS-WUHANUNIVERSITYInverterdelaycircuitLoadisresistor+capacitor,driverisresistor.36EIS-WUHANUNIVERSITYInverterdelaywithtmodeltmodel:gatedelaybasedonRCtimeconstantt.Vout(t)=VDDexp{-t/(Rn+RL)CL}90%(logic1)

10%

(logic0)tf=2.2RCL100%(logic1)

50%tD=0.69RCLForpulluptime,usepullupresistance.37EIS-WUHANUNIVERSITYtmodelinverterdelay0.5micronprocess:Rn=3.9kWCL=0.68fF延迟时间td=0.69x3.9x0.68E-15=1.8ps.上升延迟tf=2.2x3.9x0.68E-15=5.8ps.38EIS-WUHANUNIVERSITYQualityofRCapproximation39EIS-WUHANUNIVERSITYVDDVoutVin

=VDDRonCLtpHL

=f(Ron.CL)=0.69RonCLtVoutVDDRonCL10.5ln(0.5)0.3640EIS-WUHANUNIVERSITY传播延迟

——50%平均延迟时间tp=0.69CL(Reqn+Reqp)/2tpLHtpHLVOUT=0.5VDD时41EIS-WUHANUNIVERSITYRn≈1/[

n

(Vgs–Vt)]Rn∝1/

n导电因子

n=k’（W/L）k’=µnCoxCg=Cox*(W*L）42EIS-WUHANUNIVERSITYDelayasafunctionofVDD43EIS-WUHANUNIVERSITY等效电阻与W/L成反比；当VDD>>Vt+VDD/2时，等效电阻与电源无关；当VDD<=Vt时，急剧增大。IDS=βn

[(Vgs–Vt)-Vds/2]Vds44EIS-WUHANUNIVERSITY性能设计考虑

——提高速度减小负载电容增大尺寸watchoutforself-loading!提高VDD

（？)45EIS-WUHANUNIVERSITY5-5驱动大电容负载VinVoutCLVDD大电容负载off-chipload;longwireson-chip；Clockwireonchip.提高速度的措施增大尺寸带来的问题输入电容的增加前级电路负载增大46EIS-WUHANUNIVERSITY反相器的输入电容栅电容PMOS栅电容CGpNMOS栅电容CGnCin

=CGn

+CGpCin=Cox(AGn

+AGp)Cin=CoxL(Wn

+Wp)Cin=CoxLWn(1+r)=(1+r)CGn47EIS-WUHANUNIVERSITYInverterChainIfCL

isgiven:Howmanystagesareneededtominimizethedelay?Howtosizetheinverters?CLInOut48EIS-WUHANUNIVERSITYInverterDelay

Minimumlengthdevices,L=0.25mmAssumethatforWP=2WN=2Wsamepull-upandpull-downcurrentsapprox.equalresistancesRN=RPapprox.equalrisetpLHandfalltpHLdelaysAnalyzeasanRCnetworktpHL=(ln2)RNCLtpLH=(ln2)RPCLDelay(D):2WWLoadforthenextstage:49EIS-WUHANUNIVERSITYInverterwithLoadLoad(CL)DelayAssumptions:noload->zerodelayCLtp=k

RWCLRWRWWunit=1kisaconstant,equalto0.6950EIS-WUHANUNIVERSITY输出端电容构成Cout=CFET+CLtf=2.2Rn

(

CFET+CL)tr=2.2Rp

(

CFET+CL)CFET由几何图形决定51EIS-WUHANUNIVERSITYInverterwithLoadLoadDelayCintCLDelay=kRW(Cint+CL)=kRWCint+kRWCL

=kRW

Cint(1+CL/Cint)=Delay(Internal)+Delay(Load)CN=CunitCP=2Cunit2WW52EIS-WUHANUNIVERSITYDelayFormulaCint=gCgin

with

g

1f=CL/Cgin

-effectivefanoutR=Runit/W;Cint=WCunittp0=0.69RunitCunit53EIS-WUHANUNIVERSITYApplytoInverterChainCLInOut12Ntp=tp1+tp2+…+tpN54EIS-WUHANUNIVERSITYOptimalTaperingforGivenNDelayequationhasN-1unknowns,Cgin,2–Cgin,NMinimizethedelay,findN-1partialderivativesResult:Cgin,j+1/Cgin,j=Cgin,j/Cgin,j-1Sizeofeachstageisthegeometricmeanoftwoneighborseachstagehasthesameeffectivefanout(Cout/Cin)eachstagehasthesamedelay55EIS-WUHANUNIVERSITY延迟时间及级数优化Wheneachstageissizedbyfandhassameeff.fanout

f:MinimumpathdelayEffectivefanoutofeachstage:56EIS-WUHANUNIVERSITYExampleCL=8C1InOutC1CL/C1hastobeevenlydistributedacrossN=3stages:57EIS-WUHANUNIVERSITY级数优化Foragivenload,CLandgiveninputcapacitanceCinFindoptimalsizingf58EIS-WUHANUNIVERSITY级数的近似收敛解：Forg=0,f=e,N=lnFCint=g

Cgin此时，忽略自载。f=e=2.71828,N=lnF59EIS-WUHANUNIVERSITYOptimumEffectiveFanout

fOptimumfforgivenprocessdefinedbygfopt=3.6for

g=160EIS-WUHANUNIVERSITYBufferDesign111186464646442.881622.6N f tp1 64 652 8 183 4 154 2.8 15.361EIS-WUHANUNIVERSITY5-6功耗（PowerDissipation）LeadmicroprocessorspowercontinuestoincreaseP6Pentium®486386286808680858080800840040.1110100197119741978198519922000YearPower(Watts)62EIS-WUHANUNIVERSITYChipPowerDensity40048008808080858086286386486Pentium®P611010010001000019701980199020002010YearPowerDensity(W/cm2)HotPlateNuclearReactorRocketNozzleSun’sSurface…chipsmightbecomehot…Source:Borkar,DeIntel

63EIS-WUHANUNIVERSITYChipPowerDensityDistributionPowerdensityisnotuniformlydistributedacrossthechipSiliconisnotagoodheatconductorMaxjunctiontemperatureisdeterminedbyhot-spotsImpactonpackaging,coolingPowerMapOn-DieTemperature64EIS-WUHANUNIVERSITYPowerDissipationSource:Borkar,DeIntel

来源：动态功耗（DynamicPowerConsumption）ChargingandDischargingCapacitors短路电流（ShortCircuitCurrents）CircuitPathbetweenSupplyRailsduringSwitching漏电流（Leakage）Leakingdiodesandtransistors65EIS-WUHANUNIVERSITYPowerconsumptioncircuitInputissquarewave.66EIS-WUHANUNIVERSITY驱动电路i(t)=dQ/dt

，i=c*dV/dt电压不能突变，栅电压的变化有延迟时间。Q=CVC大，意味着延迟时间加长影响C的因素？P=V（C*dV/dt）=d（0.5CV2

）

/dtE=0.5CV2输入从0到VDD时，E=0.5CVDD2每次开关消耗能量。67EIS-WUHANUNIVERSITY动态功耗VinVoutCLVddAsinglecycleE=CL(VDD-VSS)2.Clockfrequencyf=1/t.EnergyE=CL(VDD-VSS)2.PowerE*f=fCL(VDD-VSS)2.影响因素

fCLVDD

其中负载消耗1/2。68EIS-WUHANUNIVERSITYEnergy/transition=CL*VDD2*P0

1Pdyn=（Energy/transition）*f=CL*VDD2*P0

1*fPdyn=CEFF*VDD2*fwhereCEFF=P01CL

f0

1Datadependent-afunctionofswitchingactivity!69EIS-WUHANUNIVERSITYConsidera0.25micronchip,500MHzclock,averageloadcapof15fF/gate(fanoutof4),2.5Vsupply.DynamicPowerconsumptionpergateis??46.875uw?

With1milliongates(assumingeachtransitionseveryclock)DynamicPowerofentirechip=??.46.875w?70EIS-WUHANUNIVERSITYLoweringDynamicPowerPdyn=CLVDD2P01fCapacitance:Functionoffan-out,wirelength,transistorsizesSupplyVoltage:HasbeendroppingwithsuccessivegenerationsClockfrequency:Increasing…Activityfactor:Howoften,onaverage,dowiresswitch?71EIS-WUHANUNIVERSITYSpeed-powerproductPower-delayproduct(PDP

）SP=P/f=CV272EIS-WUHANUNIVERSITY短路电流（ShortCircuitCurrent）IVDD

(mA)0.150.100.05Vin

(V)5.04.03.02.01.00.0VinVoutCLVdd73EIS-WUHANUNIVERSITYDurationandslopeoftheinputsignal,tscIpeakdeterminedbythesaturationcurrentofthePandNtransistorswhichdependontheirsizes,processtechnology,temperature,etc.strongfunctionoftheratiobetweeninputandoutputslopesafunctionofCLEsc/transition=tscVDD

IpeakP01Psc=tscVDD

Ipeakf0174EIS-WUHANUNIVERSITYIpeakasaFunctionofCLIpeak(A)time(sec)x10-10x10-4CL=20fFCL=100fFCL=500fF75EIS-WUHANUNIVERSITYImpactofCLonPscVinVoutCLIsc

0VinVoutCLIsc

ImaxLargecapacitiveloadSmallcapacitiveload76EIS-WUHANUNIVERSITYPscasaFunctionofRise/FallTimesPnormalizedtsin

/tsoutVDD=3.3VVDD=2.5VVDD=1.5VWhenloadcapacitanceissmall(tsin/tsout

>2forVDD>2V)thepowerisdominatedbyPscW/Lp=1.125