先进芯片封装知识介绍

OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage第一页，共33页。PackageDevelopmentTrend第二页，共33页。SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend第三页，共33页。CSPFamilyMemoryCardSiPModulePackageDevelopmentTrend第四页，共33页。3DPackage3DPackage第五页，共33页。3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP

3S-CSPS-etCSPetCSP+S-CSP

PS-fcCSP+SCSP

PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP

5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2

PoPQFN4SS-SCSP第六页，共33页。StackedDieTopdieBottomdieFOWmaterilWire第七页，共33页。TSVTSV(ThroughSiliconVia)

Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV第八页，共33页。What’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.

PoP第九页，共33页。PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology第十页，共33页。PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV™PoPTopviewBottomviewThroughMoldVia第十一页，共33页。PoP

BallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP第十二页，共33页。Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP第十三页，共33页。EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?

PiP第十四页，共33页。MaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology

PiP第十五页，共33页。MemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP

第十六页，共33页。WLCSP&FlipChipPackage第十七页，共33页。WLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.

WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.第十八页，共33页。WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.第十九页，共33页。RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.

Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).第二十页，共33页。WLCSPProcessFlowofWLCSP第二十一页，共33页。WLCSPProcessFlowofWLCSP第二十二页，共33页。FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)第二十三页，共33页。Bump第二十四页，共33页。BumpDevelopment第二十五页，共33页。BumpDevelopment第二十六页，共33页。BumpDevelopment第二十七页，共33页。C4FlipChipWhat’sC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold第二十八页，共33页。C4FlipChipBGAMainFeaturesBallPitch:0.4mm-

1.27mmPackagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912

TargetMarket: