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主板信号量测HoldCommonClockDataTransferD0D1D2D0D1D2ClockDriverDrivingReceivingTcoFlightTimeSetup1234主板信号量测DefiningTcoDinClockOutput

BufferInternal

LogicRL=50WClockrisest=0VmeasTcoLoadforTcomeasurement(fromdatabook)Tco=timefromclockrisetoVmeasintotestload主板信号量测ComponentsofTcoDinClockOutput

BufferInternal

LogicRL=50WClockrisest=0VmeasTcoInternaldelay=fromclock

risetothepointwheretheoutputbeginstoswitchExternal(buffer)delay=how

longthebuffertakestodrivethe

referenceloadtoVmeas主板信号量测ForSignalIntegrityPurposes...Output

BufferInternal

LogicnotmodeledRL=50WBufferswitchesatt=0VmeasBufferDelayLoadforTcomeasurement(fromdatabook)主板信号量测It’sallintheMath...DrivingReceivingTcoFlightTime1234???t=0主板信号量测ClockJitterClockDriverCycle1Cycle2ClockJitteroccurswhentheclockperiodvariesfromoneperiodtothenextUsuallycausedbyPLLinstabilityintheclockdriverJitterincreases/decreasestheclockperiod,decreasingtheeffectiveclockcycle主板信号量测ClockSkewD0D1D2ClockDriverD0D1D2t=0t=1t=2OccurswhendifferentdevicesseetheclocktransitionatdifferenttimesIncreases/decreasestheapparentclockcycle.Dependingonwhichdevicesaredriving/receivingReducestheeffectiveclockcycle主板信号量测BusClockCycleBudgetingForeachDriverReceiverpath:Tflightmax<ClockPeriod-Driver(Tcomax)-Skew-Jitter-Crosstalk-Receiver(Setup)Tflightmin>Receiver(Hold)-Driver(Tcomin)+Skew+CrosstalkDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)+/-Crosstalk+/-Crosstalk主板信号量测CommonClockBusExampleIntelPentium-ProreferencedesignProcessor/ChipsetBus

(GTL+,66MHz)IntelGTL+DesignGuidelines主板信号量测DefiningDeviceTimingTimingstakenfrom“AC(dynamic)Specifications”sectionsofInteldatasheetsMostdatasheetsavailableviaWWWImportantparametersClockDataValid

forGTL+BusSetup/Holdrequirements

forGTL+signalsPLLJitter(ifspec’d)PentiumPro440FX(timingsfrom440LX)主板信号量测DeterminingFlightTimesTflightmax=4.50nsTflightmin=0.45ns主板信号量测SignalWavePropagationFlighttimet1=L/cc6.5in/nsTflightmax=4.50nsTflightmin=0.45ns29in>L>3in主板信号量测Risk主板信号量测Ohm’slaw?i=(va-vb)/Rtracei→∞when

Rtrace→0主板信号量测Modeloftransmissionline主板信号量测SignalWavePropagationFlighttimet1=L/cv1=VoltagePartitionforR0&z0

R0z0

v1v2v2=VoltagePartitionforR0&RL

RL主板信号量测ImpedanceChangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhigh&pulldown主板信号量测ImpedanceChangeLayerchangeReferenceplanecrossingTracesplittingSeriescomponentConnectorPullhigh主板信号量测Schematicsvs.LayoutVcc主板信号量测MicrostripSectionhtwerZo=f(w,h,t,er)Zo=Characteristicimpedance(W)w =Widthoftrace(mils)t =Thicknessoftrace(mils)h=Thicknessofdielectriclayer(mils)er

=Dielectricconstantofthedielectriclayer

DesignedbyBoardDesignerOnlyfewoptionsavailableofferedbyPCBvendor主板信号量测ImpedanceVerificationbyTDR主板信号量测ImpedanceVerificationbyTDRImpedanceMeasuredbyHP54754A主板信号量测Flip-ChipPackage主板信号量测IBISModel

I/OBufferInformationSpec.Output

BufferInternal

Logicnotmodeled主板信号量测Simulationby3com主板信号量测LowVoltageCMOSUn-terminatedTerminated主板信号量测LowVoltageCMOSUn-terminatedTerminated主板信号量测Clockgen.Waveform主板信号量测IDEWaveform主板信号量测CrosstalkWhentracesareclosetogether,achangeincurrentflowinonetracewillcausecurrenttoflowinanadjacenttraceAggressortracesinducecurrentsinadjacentvictimtracesChangesincurrentflowonlyoccurduringtheaggressor’srisingandfallingedgesCrosstalkNoCrosstalk主板信号量测ImpactsofCrosstalkCrosstalkcausesswitchingnoisetoappearonvictimtracesthatwouldotherwisebequietCrosstalkdegradesthesystemnoisebudgetwhenitoccursbetweensignalsthatarenotpartofthesamesignalgroupSincecrosstalkonlyoccurswhendriversareswitching,themagnitudeofcrosstalkbetweenbusbitsisusuallynotimportantAggressorVictimCrosstalk-inducednoise主板信号量测ElectricalModelforCrosstalk主板信号量测Crosstalk-ImpactonBusTimingCrosstalkbetweenadjacentbusbitsaffectsedgespeed(andthereforeflighttime)Denserroutingmakesbetteruseofboardspace,butattheexpenseoflargervariationsinflighttimePre-layoutcrosstalkanalysishelpsthedesignermakethebesttradeoffbetweenroutingdensityandsignalintegrityEvenModeReferenceOddModeD0D1D2D0D1D2D0D1D2D0D1D2主板信号量测ExampleofCrosstalk主板信号量测RiskinmassproductionPCB’sstatisticalqualityDrivingstrengthvariationinchipsetPassivecomponen

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