计算机组成与结构体系英文课件：Chapter 2 – Instructions Set Architecture

ComputerOrganization&Architecture

Chapter2–InstructionsSetArchitectureContentofthislecture2.3InstructionandInstructionSequencingE.4InstructionFormats2.4AddressingModes2.6Stacks2.7Subroutines2.8AdditionalInstructions2.10CISCInstructionSets2.11RISCandCISCStyles2.3InstructionandInstructionSequencingRegisterTransferNotationAssembly-LanguageNotationRISCandCISCInstructionSetsIntroductiontoRISCInstructionSetsInstructionExecutionandStraight-LineSequencingBranchingInstructionandInstructionSequencing(1)FourTypesofInstructionsDatatransfersbetweenthememoryandtheprocessorregistersArithmeticandlogicoperationsondataProgramsequencingandcontrolI/OtransfersRegisterTransferNotationMemoryLocation:LOC,PLACE,A,VAR2ProcessorRegister:R0,R5I/OSubsystemRegister:DATAIN,OUTSTATUSThecontentsofanylocationaredenotedbyplacingsquarebracketsarounditsname:R2←[LOC]RegisterTransferNotation:R4←[R2]+[R3]TherighthandsideofanRTNexpressionalwaysdenotesavalue,andtheleft-handsideisthenameofalocationwherethevalueistobeplaced,overwritingtheoldcontentsofthatlocation.InstructionandInstructionSequencing(2)Assembly-LanguageNotationExample1:LoadR2,LOCThetransferfrommemorylocationLOCtoprocessorregisterR2Example2:AddR4,R2,R3RegistersR2andR3holdthesourceoperands,whileR4isthedestination.MnemonicsAssemblylanguagesfordifferentprocessorsoftenusedifferentmnemonicsforagivenoperation.E.g.LoadLDStoreSTRorSTInstructionandInstructionSequencing(3)RISCandCISCInstructionSetsDesignacomputerstartingbydefiningISA.Whatisinstructionsetarchitecture(ISA)?ISADefinesregistersDefinesdatatransfermodes(instructions)betweenregisters,memoryandI/OThereshouldbesufficientinstructionstoefficientlytranslateanyprogramformachineprocessingNext,defineinstructionsetformat–binaryrepresentationusedbythehardwareVariable-lengthvs.fixed-lengthinstructionsInstructionandInstructionSequencing(4)RISCandCISCInstructionSets(ctd.)TypesofISAReducedinstructionsetcomputer(RISC)Smallsetofinstructions(typically32)Simpleinstructions,eachexecutesinoneclockcycle–REALLY?Well,almost.EffectiveuseofpipeliningExample:ARMComplexinstructionsetcomputer(CISC)Manyinstructions(severalhundreds)AninstructiontakesmanycyclestoexecuteExample:IntelPentiumInstructionandInstructionSequencing(5)IntroductiontoRISCInstructionSetsTwokeycharacteristicsofRISCinstructionsetsEachinstructionfitsinasingleword.Aload/storearchitectureisused,inwhichMemoryoperandsareaccessedonlyusingLoadandStoreinstructions.Alloperandsinvolvedinanarithmeticorlogicoperationmusteitherbeinprocessorregisters,oroneoftheoperandsmaybegivenexplicitlywithintheinstructionword.InstructionandInstructionSequencing(6)IntroductiontoRISCInstructionSets(ctd.)LoadInstructionFormatLoaddestination,sourceLoadprocessor_register,memory_locationStoreInstructionFormatStoresource,destinationAddInstructionFormatAdddestination,source1,source2InstructionandInstructionSequencing(7)IntroductiontoRISCInstructionSets(ctd.)Example:C=A+BC←[A]+[B]LoadR2,ALoadR3,BAddR4,R2,R3StoreR4,CInstructionandInstructionSequencing(8)InstructionExecutionandStraight-LineSequencingExample:C=A+BC←[A]+[B]AssumethatThewordlengthis32bitsThememoryisbyte-addressableAdesiredmemoryaddresscanbedirectlyspecifiedinLoadandStoreinstructions.InstructionandInstructionSequencing(9)InstructionExecutionandStraight-LineSequencing(ctd.)Straight-lineSequencing[PC]=i[PC]=i+4…InstructionFetchInstructionExecuteInstructionandInstructionSequencing(10)BranchingAddingalistofnnumbersSeparateLoadandAddInstructionsInstructionandInstructionSequencing(11)Branching(ctd.)AddingalistofnnumbersAprogramloopBranchInstructionsLoadanewaddressintothePCBranchTargetConditionalBranchComparethecontentsoftworegistersBranch_if_[R4]>[R5]LoopConditionCodes补充内容：E.4InstructionFormatsElementsofAMachineInstructionInstructionAddressFieldFormatOpcodeFormatExampleofInstructionFormatInstructionFormats(1)WhatisMachineInstruction?Theinstructionswhichspecifytheactionsthatmustbeperformedbytheprocessorcircuitrytocarryoutthedesiredtasks.MachineCodeBinaryUsuallyrepresentedbyassemblycodes.WhatisInstructionSet?Thecollectionofdifferentmachineinstructionsthattheprocessorcanexecute.InstructionFormat(2)ElementsofAMachineInstructionOperationcodeSpecifytheoperationtobeperformed(e.g.,ADD,I/O),expressedasabinarycode.SourceoperandreferenceOperandsrequiredfortheinstructionarespecified.ResultoperandreferenceWhereshouldtheresultoftheoperationbeplaced?Sourceandresultoperandscanbeinoneofthreeareas:MainorvirtualmemoryorcacheProcessorregisterI/OdeviceInstructionFormat(3)ElementsofAMachineInstruction(ctd.)NextinstructionreferenceHow/whereisthenextinstructiontobefound.Inmostcases,thisisnotexplicitlystatedintheinstruction.Nextinstructionistheonethatlogicallyfollowsthecurrentoneintheprogram(sequential/linearprogressionthroughtheprogram).InstructionRepresentationWithinthecomputer,eachinstructionisrepresentedbyasequenceofbinarybits.InstructionFormats(4)InstructionRepresentation(ctd.)Theinstructionisdividedintofields:Operationcodefield:Specifytheoperationtobeperformed.AddressfieldInstructionDesignCriteriaShortinstructionsarebetterthanlongones.Sufficientroomintheinstructionformattoexpressalltheoperationsdesired.Numberofbitsintheaddressfield.InstructionFormats(5)InstructionAddressFieldFormatZero-addressInstructionOne-addressInstructionOP[A]→A[AC]OP[A]→ACTypically,itisunderstoodimplicitlythatasecondoperandisintheaccumulatoroftheprocessorInstructionFormat(6)InstructionAddressFieldFormat(ctd.)Two-addressInstruction[A1]OP[A2]→A1A1:DestinationoperandaddressA2:SourceoperandaddressThree-addressFormat[A1]OP[A2]→A3InstructionFormat(7)InstructionLengthFixedlength:AllinstructionshavethesamelengthVariableLength:InstructionsmaybemanydifferentlengthsInstructionFormat(8)InstructionLength(ctd.)

MethodstoReduceInstructionLengthIftheoperandistobeusedseveraltimes,itcanbemovedintoaregister.(Ifanoperandistobeusedonlyonce,puttingitinaregisterisnotworthit.)Specifyoneormoreoperandsimplicitly.InstructionFormat(9)OpcodeFormatFixed-lengthOpcodeInstructionlength:n+kbitskbitsopcodeandnbitsoperandaddressAllowsfor2kdifferentoperationsAllowsfor2naddressablememorycellsk-1bitopcodeandn+1bitaddressHalfasmanyinstructionsbuttwicetheaddressablememoryk+1bitopcodeandn-1bitaddressTwiceasmanyinstructionsbuthalftheaddressablememoryInstructionFormat(10)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)Example:Instructionlengthis16-bit,operandaddressis4-bit.Thismightbereasonableonamachinethathas16registersonwhichallarithmeticoperationstakeplace.Onedesignwouldbea4-bitopcodeandthreeaddressesineachinstruction,giving16three-addressinstructions.InstructionFormat(11)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)(ctd.)Example:Instructionlengthis16-bit,operandaddressis4-bit.(ctd.)Supposethedesignersneed:15three-addressinstructions14two-addressinstructions31one-addressinstructions16zero-addressinstructionsHowshouldwedesigntheinstructionformat?InstructionFormat(12)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)Example:(ctd.)Three-addressinstruction4-bitopcode0000–1110(15–12bit)InstructionFormat(13)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)Example:(ctd.)Two-addressinstruction8-bitopcode11110000–11111101(15–8bit)1111(15–12bit)0000–1101(11–8bit)InstructionFormat(14)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)Example:(ctd.)One-addressinstruction12-bitopcode111111100000–111111111110(15–4bit)InstructionFormat(15)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)Example:(ctd.)Zero-addressinstruction16-bitopcode1111111111110000-1111111111111111InstructionFormat(16)OpcodeFormat(ctd.)Variable-lengthOpcode(ExpandingOpcode)

SummaryExpandingOpcodesdemonstratesatrade-offbetweenspaceforOpcodeandspaceforotherinformation.CarryingvariableOpcodetoanextreme,itispossibletominimizetheaverageinstructionlengthbyencodingeveryinstructiontominimizebitsneeded.However,thiswillresultininstructionsofvarioussizesthatarenotevenalignedonbyteboundaries.ExpandingOpcodesistypicallyemployedatthebytelevelliketheaboveexample.InstructionFormat(17)ExampleofInstructionFormatInstructionFormat(18)ExampleofInstructionFormat(ctd.)2.4AddressingModesImmediateModeAbsoluteModeRegisterModeRegisterIndirectModeIndirectModeIndexMode(BasewithIndexMode)AddressingModes(1)Howtospecifywhereanoperandforaninstructionislocated?Howthebitsofanaddressfieldinaninstructionareinterpreted?WhatisAddressingModes?Thedifferentwaysinwhichthelocationofanoperandisspecifiedinaninstructionarereferredtoasaddressingmodes.AddressingModes(2)TypicalAddressingModesAddressingModes(3)ImmediateModeTheoperandisgivenexplicitlyintheinstruction.Example:

AddR4,R6,#200UsageDefineanduseconstantsSetinitialvaluesofvariablesAdvantageNomemoryreferenceotherthantheinstructionfetchisrequiredtoobtaintheoperand.DisadvantageOnlyaconstantcanbesuppliedthisway.Thesizeofthenumberislimitedbythesizeoftheaddressfield.OPOperandAddressingModes(4)AbsoluteModeTheoperandisinamemorylocation;theaddressofthislocationisgivenexplicitlyintheinstruction.Example:IntegerNUM1,NUM2,NUM3LoadR2NUM1EA=AEA:actual(effective)addressofthelocationcontainingthereferencedoperandA:contentsofanaddressfieldintheinstructionInasystemwithoutvirtualmemory,theeffectiveaddresswillbeeitheramainmemoryaddressoraregister.AddressingModes(5)AbsoluteMode(ctd.)Inavirtualmemorysystem,theeffectiveaddressisavirtualaddressoraregisteraddressUsageAccessglobalvariableswhoseaddressisknownatcompiletime.

AdvantageOnlyonememoryreferenceandnospecialcalculation.DisadvantagesTheinstructionwillalwaysaccessexactlythesamememorylocation.Itprovidesonlyalimitedaddressspace.AddressingModes(6)RegisterMode

Theoperandisthecontentsofaprocessorregister;theaddressoftheregisterisgivenintheinstruction.EA=RiRi:contentsofanaddressfieldintheinstructionthatreferstoaregister.ExampleAddR4,R2,R3UsageAccessvariableswhichareaccessedmostoftenAddressingModes(7)RegisterMode(ctd.)AdvantagesOnlyasmalladdressfieldisneededinaninstruction.Nomemoryreferencesarerequired.DisadvantageTheaddressspaceisverylimited.AddressingModes(8)RegisterIndirectModeTheeffectiveaddressoftheoperandisthecontentsofaregisterthatisspecifiedintheinstruction.EA=[Ri]AddressingModes(9)RegisterIndirectMode(ctd.)ExampleLoadR2,(R5)AddressingModes(10)RegisterIndirectMode(ctd.)Example:UsingindirectaddressingtoaccessalistofnnumbersAddressingModes(11)RegisterIndirectMode(ctd.)AdvantagesItcanreferencememorywithoutpayingthepriceofhavingafullmemoryaddressintheinstruction.Reducethememoryaccesstimes.AddressingModes(12)IndirectModeIndirectaddressingthroughamemorylocationisalsopossible,butitisfoundonlyinCISC-styleprocessors.Theeffectiveaddressoftheoperandisthecontentsofamemorylocationwhoseaddressappearsintheinstruction.EA=[A]Example:

Add(A),R0Add(A),R0BOperandABAddressingModes(13)IndirectMode(ctd.)AdvantageTheaddressspaceisverylarge.MemorywordlengthN->2NaddressspaceDisadvantageInstructionexecutionrequirestwomemoryreferencestofetchtheoperand:onetogetitsaddressandasecondtogetitsvalue.MultilevelIndirectAddressingEA=[…[A]…]Onebitofafull-wordaddressisanindirectflag(I).IftheIbitis0,thenthewordcontainstheEA.IftheIbitis1,thenanotherlevelofindirectionisinvoked.AddressingModes(14)IndexModeX(Ri)Theeffectiveaddressoftheoperandisgeneratedbyaddingaconstantvaluetothecontentsofaregister(indexregister).EA=X+[Ri]X(offset):theconstantvaluecontainedintheinstructionThecontentsoftheindexregisterarenotchangedintheprocessofgeneratingtheeffectiveaddress.AddressingModes(15)IndexMode(ctd.)TwoWaysofUsingtheIndexModeOffsetisgivenasaconstantAddressingModes(16)IndexMode(ctd.)TwoWaysofUsingtheIndexMode(ctd.)Offsetisintheindexregister.Thisformrequiresanoffsetfieldintheinstructionlargeenoughtoholdanaddress.AddressingModes(17)IndexMode(ctd.)UsageFacilitateaccesstoanoperandwhoselocationisdefinedrelativetoareferencepointwithinthedatastructureinwhichtheoperandappears.UsageExampleNrowsandfourcolumnsarrayThememoryisbyteaddressableandthewordlengthis32bits.AddressingModes(18)IndexMode(ctd.)UsageExample(ctd.)AddressingModes(19)IndexMode(ctd.)VariationsofindexaddressingBasewithindex(Ri,Rj)Asecondregister(baseregister)isusedtocontaintheoffsetX.EA=[Ri]+[Rj]BasewithindexandoffsetX(Ri,Rj)Useindexregister,baseregisterandaconstant.EA=[Ri]+[Rj]+XStacks(1)Astackisalistofdataelements,usuallywords,withtheaccessingrestrictionthatelementscanbeaddedorremovedatoneendofthelistonly.Thestructureissometimesreferredtoasapushdownstackorlast-in–first-out(LIFO)stack.PushPlaceanewitemonthestackPopRemovethetopitemfromthestackInmoderncomputers,astackisimplementedbyusingaportionofthemainmemory.ProgrammercancreateastackinthememoryThereisoftenaspecialprocessorstackaswellStacks(2)ProcessorStackProcessorhasstackpointer(SP)register

thatpointstotopoftheprocessorstackAssumeabyte-addressablememorywitha32-bitwordlengthPushoperationinvolvestwoinstructions:

Subtract SP,SP,#4

Store Rj,(SP)Popoperationalsoinvolvestwoinstructions:

Load Rj,(SP)

Add SP,SP,#4Stacks(3)ProcessorStack(ctd.)Stacks(4)ProcessorStack(ctd.)Subroutines(1)Inagivenprogram,aparticulartaskmaybe

executedmanytimesusingdifferentdataExamples:mathematicalfunction,listsortingImplementtaskinoneblockofinstructionsThisiscalledasubroutineRatherthanreproduceentiresubroutineblockineachpartofprogram,useasubroutinecallSpecialtypeofbranchwithCallinstructionSubroutines(2)Branchingtosameblockofinstructions

savesspaceinmemory,butmustbranchbackThesubroutinemustreturntocallingprogramafterexecutinglastinstructioninsubroutineThisbranchisdonewithaReturninstructionSubroutineLinkageSubroutinecanbecalledfromdifferentplacesHowcanreturnbedonetocorrectplace?ThisistheissueofsubroutinelinkageSubroutines(3)SubroutineLinkage(ctd.)DuringexecutionofCallinstruction,PCupdatedtopointtoinstructionafterCallSavethisaddressforReturninstructiontouseSimplestmethod:placeaddressinlinkregisterCallinstructionperformstwooperations:storeupdatedPCcontentsinlinkregister,thenbranchtotarget(subroutine)addressReturnjustbranchestoaddressinlinkregisterSubroutines(4)SubroutineLinkage(ctd.)Subroutines(5)SubroutineNesting&TheProcessorStackWecanpermitonesubroutinetocallanother,whichresultsinsubroutinenesting.Linkregistercontentsafterfirstsubroutinecallareoverwrittenaftersecondsubroutinecall.Firstsubroutineshouldsavelinkregisterontheprocessorstackbeforesecondcall.Afterreturnfromsecondsubroutine,firstsubroutinerestoreslinkregister.Subroutinenestingcanbecarriedouttoanydepth.Returnaddressesaregeneratedandusedinalast-in–first-outorder.Thissuggeststhatthereturnaddressesassociatedwithsubroutinecallsshouldbepushedontotheprocessorstack.2.8AdditionalInstructionsLogicInstructionsShiftandRotateInstructionsMultiplicationandDivisionAdditionalInstructions(1)LogicInstructionsAND,OR,andNOToperationsonsinglebits

arebasicbuildingblocksofdigitalcircuits.Similaroperationsinsoftwareonmultiplebits.UsingRISC-styleinstructions,alloperandsare

inregistersorspecifiedasimmediatevalues:

Or R4,R2,R3

And R5,R6,#0xFF8-bitimmediateiszero-extendedto32bitsAdditionalInstructions(2)LogicInstructions(ctd.)SupposethatfourASCIIcharactersarecontainedinthe32-bitregisterR2.Insometask,wewishtodetermineiftherightmostcharacterisZ.TheASCIIcodeforZis01011010,whichisexpressedinhexadecimalnotationas5A.AndR2,R2,#0xFFMoveR3,#0x5ABranch_if_[R2]=[R3]FOUNDZAdditionalInstructions(3)ShiftandRotateInstructionsShiftingbinaryvalueleft/right=mult/divby2LogicalShiftsForgeneraloperands,weusealogicalshift.LogicShiftingLeft(LShiftL)LShiftLRi,Rj,countShiftthecontentsofregisterRjleftbyanumberofbitpositionsgivenbythecountoperand,andplacestheresultinregisterRi,withoutchangingthecontentsofRj.LogicShiftingRight(LShiftR)AdditionalInstructions(4)ShiftandRotateInstructions(ctd.)LogicalShifts(ctd.)AdditionalInstructions(5)ShiftandRotateInstructions(ctd.)Digit-PackingExampleIllustrateshift,logic,byte-accessinstructionsMemoryhastwobinary-codeddecimaldigitsPointersetto1stbyteforindex-modeaccesstoload1stdigit,whichisshiftedtoupperbitsUpperbitsof2nddigitareclearedbyANDingORingcombines2nddigitwithshifted1stdigitforresultoftwopackeddigitsinasinglebyte32-bitregisters,butonly8lowestbitsrelevantAdditionalInstructions(6)ShiftandRotateInstructions(ctd.)Digit-PackingExample(ctd.)AdditionalInstructions(7)ShiftandRotateInstructions(ctd.)ArithmeticShiftsInanarithmeticshift,thebitpatternbeingshiftedisinterpretedasasignednumber.Onarightshiftthesignbitmustberepeatedasthefill-inbitforthevacatedpositionasarequirementofthe2’s-complementrepresentationfornumbers.AdditionalInstructions(8)ShiftandRotateInstructions(ctd.)RotateOperationsRotateleftwithoutcarryAdditionalInstructions(9)ShiftandRotateInstructions(ctd.)RotateOperations(ctd.)RotateleftwithcarryAdditionalInstructions(10)ShiftandRotateInstructions(ctd.)RotateOperations(ctd.)RotaterightwithoutcarryAdditionalInstructions(11)ShiftandRotateInstructions(ctd.)RotateOperations(ctd.)RotaterightwithcarryAdditionalInstructions(12)MultiplicationandDivisionSignedintegermultiplicationofn-bitnumbersproducesaproductwithasmanyas2nbitsProcessortruncatesproducttofitinaregister:

Multiply Rk,Ri,Rj (Rk[Ri][Rj])Forgeneralcase,2registers(RkandR(k+1)mayholdresultIntegerdivisionproducesquotientasresult:

Divide Rk,Ri,Rj (Rk[Ri]/[Rj])RemainderisdiscardedorplacedinaregisterR(k+1)2.10CISCInstructionSetsAdditionalAddressingModesConditionCodesCISCInstructionSets(1)CISCinstructionsetsarenotconstrainedtotheload/storearchitecture,inwhicharithmeticandlogicoperationscanbeperformedonlyonoperandsthatareinprocessorregisters.CISCinstructionsdonotnecessarilyhavetofitintoasingleword.Someinstructionsmayoccupyasingleword,butothersmayspanmultiplewords.Mostarithmeticandlogicinstructionsusethetwo-addressformat.Operationdestination,sourceExample:AddB,APerformstheoperationB←[A]+[B]onmemoryoperands.CISCInstructionSets(2)TheMoveinstructionincludesthefunctionalityoftheLoadandStoreinstructionsMovedestination,sourceExampleC=A+BMoveC,BAddC,AInsomeCISCprocessorsoneoperandmaybeinthememorybuttheothermustbeinaregister.MoveRi,AAddRi,BMoveC,RiCISCInstructionSets(3)AutoincrementandAutodecrementModeAutoincrementModeTheeffectiveaddressoftheoperandisthecontentsofaregisterspecifiedintheinstruction.Afteraccessingtheoperand,thecontentsofthisregisterareautomaticallyincrementedtopointtothenextiteminalist.(Ri)+EA=[Ri]IncrementRiUsefulforadjustingpointersinloopbody:

Add SUM,(Ri)

MoveByte (Rj),RkIncrementby4forwords,andby1forbytesCISCInstructionSets(4)AutoincrementandAutodecrementMode(ctd.)AutodecrementModeThecontentsofaregisterspecifiedintheinstructionarefirstautomaticallydecrementedandarethenusedastheeffectiveaddressoftheoperand.−(Ri)Useautoinc.&autodec.forstackoperations:

Move(SP),NEWITEM (push)

MoveITEM,(SP) (pop)CISCInstructionSets(5)RelativeModeTheeffectiveaddressisdeterminedbytheIndexmodeusingtheprogramcounterinplaceofthegeneral-purposeregisterRi.EA=[PC]+X,XisasignednumberUsageAccessdataoperandSpecifythetargetaddressinbranchinstructions.Example

Branch>0LoopThebranchtargetlocationcanbecomputedbyspecifyingitasanoffsetfromthecurrentvalueoftheprogramcounter.CISCInstructionSets(6)ConditionCodesProcessorcanmaintaininformationonresultstoaffectsubsequentconditionalbranchesResultsfromarithmetic/comparis