海思综合脚本

1、*“ 个个个个个个#Copyright(c) 2005,Huawei Technologies Co.,Ltd.#All Rirht Reserved# #Project name : SD3550#File name : syn_itrans.tcl#Author: hechenghong#ID:40506#Email: HYPERLINK mailto:hechenghong hechenghong#Abstract : syntesis script for ITRANS# #Modification History#$Log: syn_itrans.tcl,v $#Revision 1

2、.5 2005/05/12 02:27:55 h40506 #no message# #Revision 1.4 2005/05/12 02:15:39 h40506#no message#Revision 1.3 2005/05/09 03:43:33 h40506 #no message# #Revision 1.2 2005/05/06 04:01:26 h40506#no message#Revision 1.1 2005/05/05 10:24:37 h40506 #no message#*“ “ “ “ “ 个个个个个sh date remove_design -designs #

3、 #clk variables# set CLK_VCORE_PER 7 set CLK_SETUP_SKEW0.2set CLK_HOLD_SKEW0.1set CLK_TRANSITION0.4set CLK_OUT_LATENCY0set maximum_fan_out 16set MAXIMUM_TRANSITION 0.5set CLK_ZSP_PER4.5set CLK_CORE_IDLYset CLK_CORE_ODLYexpr 0.8*$CLK_VCORE_PERexpr 0.8*$CLK_VCORE_PER#environment info #*SMIC#set max_li

4、brary sm13ugfsdsc_ss#set max_op_cond WC_TIMING#set min_library sm13ugfsdsc_ff#set min_op_cond BC_TIMING#set std_drv_cell SDN_INV_1#set std_load load_of $max_library/SDN_INV_1/X#*RISANset max_library slow_1v08c125set max_op_cond slow_1v08c125set min_library fastset min_op_cond fastset std_drv_cell IN

5、VX1set std_load load_of $max_library/INVX1/Y#Compile variables #set test_default_scan_style multiplexed_flip_flop#Paths variables #set jjbo_dir /project2/SD592/jjboset main_dir ././././set RTL_ROOT_PATH $main_dir/asic/rtlset NETLIST_PATH $main_dir/asic/flow/syn/netlistset RPT_PATH $main_dir/asic/syn

6、/logset DB_PATH$main_dir/asic/syn/db# #void warning Info # # suppress_message VER_130 suppress_message VER_129 suppress_message VER_318 suppress_message ELAB_311 suppress_message VER_936#read&link&Check design # TOC o 1-5 h z read_verilog list $RTL_ROOT_PATH/public/def.v$RTL_ROOT_PATH/public/uudiv.v

7、$RTL_ROOT_PATH/itrans/acdc.v$RTL_ROOT_PATH/itrans/iscan_ctrl.v$RTL_ROOT_PATH/itrans/iscanram_ctrl.v$RTL_ROOT_PATH/itrans/iscan.v$RTL_ROOT_PATH/itrans/ihdm4_1d.v$RTL_ROOT_PATH/itrans/iq_cal.v$RTL_ROOT_PATH/itrans/iq.v$RTL_ROOT_PATH/itrans/iq_cal.v$RTL_ROOT_PATH/itrans/iq.v$RTL_ROOT_PATH/itrans/idct4_

8、1d.v$RTL_ROOT_PATH/itrans/idct4_1wmv.v$RTL_ROOT_PATH/itrans/idct4_2wmv.v$RTL_ROOT_PATH/itrans/idct8_1d.v$RTL_ROOT_PATH/itrans/idct8_1wmv.v$RTL_ROOT_PATH/itrans/idct8_2wmv.v$RTL_ROOT_PATH/itrans/idct.v$RTL_ROOT_PATH/itrans/rsd_buf.v$RTL_ROOT_PATH/itrans/itrans_ram.v$RTL_ROOT_PATH/itrans/itrans.v set

9、top ITRANScurrent_design $topset_auto_disable_drc_nets -constant falselinkcheck_design $RPT_PATH/$top.chkdesign uniquify#Define IO port name#set clk_vencget_ports clkset rst_vencget_ports rst_nset general_inputs remove_from_collection all_inputs $clk_vencset general_inputs remove_from_collection $ge

10、neral_inputs $rst_vencset no_dly_inputs get_ports cbpyset all_dly_inputs remove_from_collection $general_inputs $no_dly_inputs #set_constraints#1 Set design environment#set_operating_conditions -library $max_library $max_op_cond set auto_wire_load_selection trueset_fix_multiple_port_nets -allset_dri

11、ving_cell -lib_cell $std_drv_cell -library $max_library -no_design_rule $general_inputsset_load expr 20 * $std_load all_outputs#2 Set design rule constraints#set_max_fanout 4 $general_inputsset_max_transition $MAXIMUM_TRANSITION get_designs $top#3 Set area constraint#set_max_area 0#4 Set constraints

12、 for clock signalscreate_clock -n clk_name $clk_venc -period $CLK_VCORE_PER -wave list 0 expr $CLK_VCORE_PER/2set_clock_uncertainty -setup $CLK_SETUP_SKEW get_clocks clk_nameset_clock_uncertainty -hold $CLK_HOLD_SKEW get_clocks clk_name set_clock_transition $CLK_TRANSITON get_clocks clk_nameset_cloc

13、k_uncertainty hold $CLK_HOLD_SKEW get_clocks clk_nameset_clock_transition $CLK_TRANSITION get_clocks clk_nameset_clock_latency $CLK_OUT_LATENCY get_clocks clk_name set_dont_touch_network get_clocks clk_name set_drive 0 $clk_venccurrent_design $top#5 Set constraints for reset signals-#set_dont_touch_

14、network $rst_vencset_drive 0 $rst_vencset_ideal_net get_nets all_connected $rst_venc#6 Set input delay and output delay-#set_input_delay -clock clk_name $CLK_CORE_IDLY $general_inputsset_input_delay -clock clk_name $CLK_CORE_IDLY $all_dly_inputsset_output_delay -clock clk_name $CLK_CORE_IDLY $all_ou

15、tputs#7 Set multicycle#8#set_false_path -from venc_rst_nset_false_path -from $rst_venc# compile_design#1 compile medium#*SMIC#set_dont_use sm1 3ugfsdsc_ss/SDN_DEL_R*_*#*RTSANset_dont_use slow_1v08c125/DLY*set_dont_use slow_1v08c125/*DFF*SR*set_dont_use slow_1v08c125/*DFF*Q*set_dont_use slow_1v08c125

16、/CLKBUFX*set_dont_use slow_1v08c125/CLKINVX*set_dont_use slow_1v08c125/SEDFF*set_dont_use slow_1v08c125/EDFF*set_dont_use slow_1v08c125/MDFF*curremt_design $topcompile -scan -map_effort medium#2 compile increamentcurrent_design $topforeach_in_collection design_name get_designs * current_design $desi

17、gn_name nullredirect null set dw_cell_list filter find cell *is_synlib_operator = true | is_synlib_module = true | is_dw_subblock =true if $dw_cell_list != list set_ungroup $dw_cell_list truecurrent_design $stopcompile -increment#write *.db and *.v#current_design $topdefine_name_rules simple_names -

18、maps ( *cell*”,”V,*-return”,RET change_names -rule simple_names -hierchange_names -rules verilog -hierwrite -f db -hier -output $DB_PATH/$top.db $topwrite -f verilog -hier -output $NETLIST_PATH/$top.v $top#generate reports #0check_design $RPT_PATH/$top.check_rptcheck_timing $RPT_PATH/$top.check_rpt#1report_constraint -all -max_delay -max_fanout -max_tran