教程adi tigersharc培训ts201处理器l1

1、Link Ports2Links ControllerIFIFOOFIFOOBUFBus Interface UnitDMA ControllerLinks ControllerINTERNALBUSDataAddressControl4 independent Link PortsControl RegStatus RegTCBs128-bit DATA32-bit ADDRI/O ProcessorDMARS-busDMArequests3Link Port - OverviewTigerSHARC optional communication channel Designed speci

2、fically for point to point communication between TigerSHARCsCan be used between any other device designed to LP protocolThroughputEach link port can transfer data at up to 500Mbytes/secTransfer Control (transfers quad-words only)Core - through interrupts or pollingDMA - through dedicated link port t

3、ransmit and receive DMA channelsBootingLinks can also be used for boot - on reset all link channels are initialized to receive 256 words and deliver them to internal memory block 0 beginning at address 0.4Links ControllerLBUFTX Shift Register LBUFRX Shift Register PHYLinks PortsSOC BusShift register

4、s are one quad word wideLinks ArchitectureLBUFTX and LBUFRX registers are double buffered memory mapped UREGSShift registers are not accessible by softwarePHY5Physical Interface PinsFour Link Ports with Receive and Transmit section eachPinsLxDATO3:0LVDS 4-bit uni-directional data pins LxDATI3:0LVDS

5、4-bit uni-directional data pins LxCLKOUTLVDS clock output pin LxCLKINLVDS clock input pin LxACKOUTLVTTL handshake outputLxACKINLVTTL handshake input POLVTTL block completion out PILVTTL block completion inProtocolData is driven and latched on both the rising and falling edge of link clock6Transmitti

6、ng and ReceivingCore driven transfer is performed byCore writing quad-word data to the LBUFTX registerCore reading quad-word data from the LBUFRX registerDMA driven transferTwo DMA channels per Link Port, one Tx and one RxLink port DMArequires Transfer Control Block (TCB) for Tx or Rxonly quad-word

7、transfers are allowedDMA Link Port (cross) chaining is supported7Transfer Modes4bit high throughput mode1bit minimum wireing mode8Connection Diagram9LVDS Connectivity near connection10LVDS Connectivity far connection11Control RegistersLRCTLx Link Receive Control RegisterLTCTLx Link Transmit Control

8、Register 31 : 543210RESERVEDDSIZEBCMPERTOEVERELRENLREN -Receive EnableVERE -Verification EnableRTOE -Receive Timeout EnableBCMPE - Block Completion signalling enableDSIZE -pin width used for transmission31 : 1211 : 876 : 543210RESRESSPDDSIZEBCMPETTOEVERELTENLTEN -Transmit EnableVERE -Verification EnableTTO