EDA数字钟程序代码1

第页--分频器libraryieee;useieee.std_logic_1164.all;entityfenpinisport(clk:instd_logic;qH:bufferstd_logic;qout:bufferstd_logic);endentity;architecturec20offenpinisbeginprocess(clk)variablenum:integer:=1;variablenum1:integer:=1beginifclk'eventandclk='0'thenif(num=2)--0000000)--1HZ--10000000totimerthennum:=1;qout<=notqout;elsenum:=num+1;endif;if(num1=1)--000000)--1000HZ--10000toweithennum1:=1;qH<=notqH;elsenum1:=num1+1;endif;endif;endprocess;endc20;--timerlibraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityClock3isport(clk:instd_logic;duan:outstd_logic_vector(3downto0);wei:instd_logic_vector(2downto0);wei2:outstd_logic_vector(2downto0)endentity;architecturecloofClock3issignalclk2:std_logic;signalkeys:std_logic_vector(2downto0);beginkeys<=key_h&key_m&key_s;clk2<=clkorflag;process(key_que)beginifkey_que'eventandkey_que='0'thenflag<=notflag;endif;endprocess;process(clk2,keys)--如果用拨码开关，就将clk2改为clkbegincaseflagiswhen'0'=>ifclk2'eventandclk2='0'then正常计时ifscn=59andmin=59andhor=23thenscn:=0;min:=0;hor:=0;elsifscn=59andmin=59thenscn:=0;min:=0;hor:=hor+1;elsifscn=59thenscn:=0;min:=min+1;elsescn:=scn+1;endif;ifmin=59整点报时500hzthenifscn=50orscn=52orscn=54orscn=56orscn=58thenmusic_out<=musicL;elsemusic_out<='0';endif;elsifmin=0andscn=0整点报时1000HZthenmusic_out<=musicH;elsemusic_out<='0';endif;endif;when'1'=>casekeysiswhen"011"=>ifhor=23thenhor:=0;elsehor:=hor+1;endif;--keys<="00";when"101"=>ifmin=59thenmin:=0;elsemin:=min+1;endif;--keys<="00";when"110"=>ifscn=59thenscn:=0;elsescn:=scn+1;endif;--keys<="00";whenothers=>null;--keys<="00";endcase;endcase;h:=hor/10;--除法，特别是取余数运算会占用很多逻辑资源hH<="0000"+h;hL<="0000"+(hor-10*h);m:=min/10;mH<="0000"+m;mL<="0000"+(min-10*m);s:=scn/10;sH<="0000"+s;sL<="0000"+(scn-10*s);endprocess;endclo;去抖libraryieee;--去抖电路useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityqudouisport(clk,key_in:instd_logic;key_out:outstd_logic);endentity;architecturekey_qudouofqudouisbeginprocess(clk)--5msvariablenum:integer:=0;variables:integer:=0;beginifclk'eventandclk='0'thencasesiswhen0=>key_out<='1';ifkey_in='0'thennum:=num+1;--用状态机思路更清晰，但是程序体积更庞大ifnum=3thennum:=0;s:=1;endif;elsenum:=0;endif;when1=>key_out<='0';ifkey_in='1'thens:=0;endif;whenothers=>null;endcase;endif;endprocess;key_qudou;--顶层文件libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityClockisport(clk:instd_logic;music_out:outstd_logic;key_in:instd_logic;keyh_in:instd_logic;keym_in:instd_logic;keys_in:instd_logic;duan:outstd_logic_vector(6downto0);wei:bufferstd_logic_vector(2downto0));endentity;architecturecloofClockiscomponentfenpinport(clk:instd_logic;musicH:bufferstd_logic;musicL:bufferstd_logic;qH:bufferstd_logic;qM:bufferstd_logic;qout:bufferstd_logic);endcomponent;componentcounter_8port(clk:instd_logic;count:bufferstd_logic_vector(2downto0));endcomponent;componentClock3port(clk:instd_logic;key_que:instd_logic;key_h:instd_logic;key_m:instd_logic;key_s:instd_logic;musicH:instd_logic;musicL:instd_logic;music_out:outstd_logic;duan:outstd_logic_vector(3downto0);wei:instd_logic_vector(2downto0);wei2:outstd_logic_vector(2downto0)endcomponent;componentseg7decport(din:instd_logic_vector(3downto0);qout:outstd_logic_vector(6downto0));--a,b,c...f,gendcomponent;componentqudouport(clk,key_in:instd_logic;keyh_in:instd_logic;keym_in:instd_logic;keys_in:instd_logic;key_out:outstd_logic;keyh_out:outstd_logic;keym_out:outstd_logic;keys_out:outstd_logic);endcomponent;beginu1:fenpinportmap(clk=>clk,qH=>clkH,qout=>clkL,qM=>clkM,musicH=>c_m_H,musicL=>c_m_L);u2:counter_8portmap(clk=>clkH,count=>wei_in);u3:seg7decportmap(din=>duan_in,qout=>duan);u4:Clock3portmap(clk=>clkL,duan=>duan_in,w