半导体集成电路-第2章集成电路的基本制造工艺

半导体集成电路上节课内容要点双极集成电路的基本工艺双极集成电路中元件结构2023/10/13pn+n-epin+P-Sin+-BLCBESP+P+双极集成电路的基本工艺2023/10/13P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四层三结结构的双极晶体管双极集成电路中元件结构2023/10/13ECB相关知识点隐埋层的作用、电隔离的概念、寄生晶体管本节课内容

MOS集成电路的工艺

P阱CMOS工艺

BiCMOS集成电路的工艺

N阱CMOS工艺双阱CMOS工艺2023/10/13MOS晶体管的动作

MOS晶体管实质上是一种使电流时而流过，时而切断的开关n+n+P型硅基板栅极（金属）绝缘层（SiO2）半导体基板漏极源极N沟MOS晶体管的基本结构源极(S)漏极(D)栅极(G)MOSFET的基本结构2023/10/13siliconsubstratesourcedraingateoxideoxidetopnitride氮化物metalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongate多晶硅栅dopedsilicon掺杂硅fieldoxidegateoxideMOS晶体管的立体结构2023/10/13在硅衬底上制作MOS晶体管siliconsubstrate2023/10/13siliconsubstrateoxidefieldoxide2023/10/13siliconsubstrateoxidePhotoresist光刻胶2023/10/13ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmask铬镀金的玻璃屏UltravioletLight紫外线siliconsubstrateoxide2023/10/13非感光区域siliconsubstrate感光区域oxidephotoresist2023/10/13Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist显影2023/10/13siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蚀2023/10/13siliconsubstrateoxideoxidesiliconsubstratefieldoxide去胶2023/10/13siliconsubstrateoxideoxidegateoxidethinoxidelayer2023/10/13siliconsubstrateoxideoxidePolysilicon多晶硅gateoxide2023/10/13siliconsubstrateoxideoxidegategateultra-thin超薄

gateoxidepolysilicongate2023/10/13siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeam离子束扫描方向implantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2023/10/13siliconsubstrateoxideoxidegategatesourcedraindopedsilicon掺杂硅2023/10/13自对准工艺在有源区上覆盖一层薄氧化层淀积多晶硅，用多晶硅栅极版图刻蚀多晶硅以多晶硅栅极图形为掩膜板，刻蚀氧化膜离子注入2023/10/13siliconsubstratesourcedraingate2023/10/13siliconsubstrategatecontactholes接触孔drainsource2023/10/13siliconsubstrategatecontactholesdrainsource2023/10/13完整的简单MOS晶体管结构siliconsubstratesourcedraingateoxideoxidetopnitride氮化物metalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongate多晶硅栅dopedsiliconfieldoxidegateoxide2023/10/13CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2023/10/13主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2023/10/13掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2023/10/13具体步骤如下：1．生长二氧化硅（湿法氧化）：Si(固体)+2H2OSiO2（固体）+2H22023/10/13氧化2023/10/132．P阱光刻：涂胶腌膜对准曝光光源显影2023/10/132023/10/13硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-well3．P阱掺杂：2023/10/132023/10/13离子源高压电源电流积分器离子束2023/10/13掩膜2：光刻有源区有源区：nMOS、PMOS

晶体管形成的区域P+N+N+P+N-SiP-wellP-wellP-well淀积氮化硅光刻有源区场区氧化去除有源区氮化硅及二氧化硅SiO2隔离岛2023/10/13有源区depositednitridelayer有源区光刻板N型p型MOS制作区域(漏-栅-源)2023/10/13P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-well氮化膜生长P-well涂胶P-well对版曝光有源区光刻板2.光刻有源区：2023/10/13P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P-well场区氧化（湿法氧化）P-well去除氮化硅薄膜及有源区SiO22023/10/13掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区SiO2P-wellP+N+N+P+N-SiP-well栅极氧化膜多晶硅栅极生长栅极氧化膜淀积多晶硅光刻多晶硅2023/10/13P-well生长栅极氧化膜P-well淀积多晶硅P-well涂胶光刻多晶硅光刻板P-well多晶硅刻蚀2023/10/13掩膜4

：P+区光刻

1、P+区光刻

2、离子注入B+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+2023/10/13P-wellP+P-wellP+P+硼离子注入去胶2023/10/13掩膜5

：N+区光刻

1、N+区光刻

2、离子注入P+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2023/10/13P-wellN+P-wellP+P+磷离子注入去胶P+P+N+N+2023/10/13掩膜6

：光刻接触孔1、淀积PSG.2、光刻接触孔3、刻蚀接触孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2023/10/13掩膜6

：光刻接触孔P-wellP+P+N+N+淀积PSGP-wellP+P+N+N+光刻接触孔P-wellP+P+N+N+刻蚀接触孔P-wellP+P+N+N+去胶2023/10/132023/10/13掩膜7

：光刻铝线1、淀积铝.2、光刻铝3、去胶P-wellP-wellP+P+N+N+2023/10/13P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P-wellN-型硅极板多晶硅N+区2023/10/13Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2023/10/13InterconnectImpactonChip2023/10/13掩膜8

：刻钝化孔CircuitPADCHIP双阱标准CMOS工艺P+p-epipwellnwellp+n+gateoxideAl(Cu)tungstenSiO2SiO2TiSi2fieldoxide增加器件密度防止寄生晶体管效应（闩锁效应）p-epiP阱n+STITiSi2STI深亚微米CMOS晶体管结构STISTISTIN阱n-n+n-p+p-p+p-源/漏扩展区浅槽隔离侧墙多晶硅硅化物2023/10/13功耗驱动能力CMOS双极型Bi-CMOSBiCMOS集成电路工艺2023/10/13BiCMOS工艺分类以CMOS工艺为基础的BiCMOS工艺以双极工艺为基础的BiCMOS工艺。2023/10/13以P阱CMOS工艺为基础的BiCMOS工艺NPN晶体管电流增益小；集电极的串联电阻很大;NPN管C极只能接固定电位，从而限制了NPN管的使用2023/10/13以N阱CMOS工艺为基础的BiCMOS工艺NPN具有较薄的基区，提高了其性能；N阱使得NPN管C极与衬底隔开，可根据电路需要接电位集电极串联电阻还是太大，影响双极器件的驱动能力在现有N阱CMOS工艺上增加一块掩膜板2023/10/13

以N阱CMOS工艺为基础的改进BiCMOS工艺使NPN管的集电极串联电阻减小5

6倍；使CMOS器件的抗闩锁性能大大提高2023/10/13三、后部封装（在另外厂房）（1）背面减薄（2）切片（3）粘片（4）压焊：