北科大数字电子技术生教学课件授课de09wu

DigitalFundamentalsCHAPTER9

ShiftRegisters（移位寄存器）9-1BasicShiftRegisterFunctions

（基本移位寄存器功能）Shiftregistersconsistofarrangementsofflip-flopsandareimportantinapplicationsinvolvingthestorageandtransferofdatainadigitalsystem.Eachstage(flip-flop)representsonebitofstoragecapacity,thenumberofstagesofaregisterdeterminesitsstoragecapacityTheconceptofstoringa1or0IaDflip-flopDatainDatainDatainDatainDatainDataoutDataoutDataoutDataoutDataoutSerialin/shiftright/serialoutSerialin/shiftleft/serialoutParallelin/serialoutParallelin/paralleloutSerialin/paralleloutRotaterightRotateleftThetypesofdatamovementinshiftregisterTheshiftcapabilityofaregisterpermitsthemovementofdatafromstagetostagewithintheregisterorintooroutofaregisteruponapplicationofclockpulse9-2SerialIn/SerialOutShiftRegisters Acceptsdataserially ProducesthestoredinformationonitsoutputalsoinserialformA4-bitserialin/serialoutshiftregisterimplementedwithDflip-flops11111CLKCLKCLKCLKEachclockpulsewillmoveaninputbittothenextflip-floptheentryoffourbits1010intotheregisterBeginwiththeright-mostbitThesedatacanbestoredforanylengthoftimeaslongastheflip-flopshavedcpowerEachclockpulsewillmoveaninputbittothenextflip-flop.thefourbits(1010)beingseriallyshiftedoutoftheregisterExample9-1Showthestatesofthe5-bitregisterforthespecifieddatainputandclockwaveforms.Assumethattheregisterisinitiallycleared(all0s).P366Logicsymbolforan8-bitserialin/serialoutshiftregister“SRG8”designationindicatesashiftregisterwithan8-bitcapacityExercise（P396：8）Determinethedata-outputwaveform.(Assumethattheregisterisinitiallycleared)9-3SerialIn/ParallelOutShiftRegisters Acceptsdataserially TheoutputofeachstageisavailableatthesametimeLogicsymbolA4-bitserialin/paralleloutshiftregistercanbeusedtoconvertserialdatatoparallelformA8-bitserialin/paralleloutIC:74HC164Oneofthetwoserialdatainputs(A,B)canbeusedasanactiveHIGHenabletogatetheotherinput.Sampletimingdiagramfora74HC1649-4ParallelIn/SerialOutShiftRegistersLogicsymbolAcceptsdatasimultaneouslyProducesthestoredinformationonitsoutputinserialformcanbeusedtoconvertparalleldatatoserialformWhenSHIFT/LOADisLOW,gatesG1~G3areenabled,allowingeachdatabittobeappliedtotheDinputofitsrespectiveflip-flop.WhenSHIFT/LOADisHIGH,

gatesG4~G6areenabled,allowingthedatabitstoshiftrightfromonestagetothenext.A4-bitparallelin/serialoutshiftregisterExample9-3:Showthedataoutputwaveformfora4-bitregisterwiththeinputsinthefigure.P371A8-bitparallelloadIC:74HC165TheclockcanbeinhibitedanytimewithaHIGHonthe“CLKINH”input9-5ParallelIn/ParallelOutShiftRegistersA4-bitparallel-accessshiftregisterIC:74HC195JandKaretheserialdatainputstothefirststageoftheregister(Q0)Sampletimingdiagramfor74HC1959-6BidirectionalShiftRegisters Thedatacanbeshiftedeitherleftorrightdependonthelevelofacontrolline.4-bitbidirectionalshiftregisterRIGHT/LEFT=HIGH:shiftrightRIGHT/LEFT=LOW:shiftleftExample9-4:DeterminetheoutputsinFigure9-19.(AssumetheserialdatainputlineisLOW)P353:CLK1CLK2CLK3CLK4CLK5CLK6CLK7CLK8CLK9Q0isontheleft4-bituniversalIC:74HC194AuniversalshiftregisterhasbothserialandparallelinputandoutputcapabilityModecontrolinputsSampleTimingDiagramof74HC194Example:P370-22DeterminetheQoutputsofa74HC194withtheinputsshown.(InputsD0、D1、D2and

D3areallHIGH)P372-21Usetwo74HC194tocreatean8-bitbidirectionalshiftregisterExercise:P372-21Usetwo74HC194tocreatean8-bitbidirectionalshiftregisterExercise:9-7ShiftRegisterCounters

（移位寄存器型计数器）9-7-1TheJohnsonCounter （扭环形计数器）9-7-2TheRingCounter （环形计数器）Ashiftregistercounterisbasicallyashiftregisterwiththeserialoutputconnectedbacktotheserialinputtoproducespecialsequences.9-7-1TheJohnsonCounter9-7-1TheJohnsonCounter“twisted-ring”counter9-7-1TheJohnsonCounter1)Excitationequation2)Nextstateequation9-7-1TheJohnsonCounter2)Nextstateequation3)StateconversiontableCLK Q0

Q1

Q2

Q30123456700001 0001100111011110111001100019-7-1TheJohnsonCounter3)StateconverttableCLK Q0

Q1

Q2

Q30123456700001 000110011101111011100110001Ingeneral,aJohnsoncounterwillproduceamodulusof2n,wheren=numberofstagesinthecounterTimingsequencefora5-bitJohnsoncounterTheringcountercanalsobeimplementedwitheitherDflip-flopsorJ-Kflip-flops.9-7-2TheRingCounter9-7-2TheRingCounterTheringcountermustbepreloadedwiththedesiredpattern(usuallyasingle0or1)NextstateequationThe10-bitRingCounterThewaveformsforan8-bitringcounterwithasingle1ARingCounterusingIC:74HC195shiftregister9-8ShiftRegisterApplications

（移位寄存器的应用）Shiftregisterscanbeusedtodelayadigitalsignalbyapredeterminedamount.TimeDelayAn8-bitserialin/serialoutshiftregisterhasa40MHzclock.Whatisthetotaldelaythroughtheregister?Thedelayforeachclockis1/40MHz=25nsThetotaldelayis8x25ns=200ns25ns=200nsExercise:P382:Example9-6

DeterminetheamountoftimedelaybetweentheserialinputandeachoutputSerial-to-ParallelDataConverterP384UniversalAsynchronousReceiverTransmitter(UART通用异步收发报机)

UATRinterfaceUniversalAsynchronousReceiverTransmitter(UART)

BasicUARTblockdiagramKeyboardEncoder1.Theshiftregisterthatwouldbeusedtodelayserialdataby4clockperiodsis a. c. b. d.QuizQuiz2. Thecircuitshownisa a.serial-in/serial-outshiftregister

b.serial-in/parallel-outshiftregister c.parallel-in/serial-outshiftregister d.parallel-in/parallel-outshiftregisterQuiz3. IftheSHIFT/LOADlineisHIGH,data a.isloadedfromD0,D1,D2andD3immediately b.isloadedfromD0,D1,D2andD3onthenextCLK c.shiftedfromlefttorightonthenextCLK

d.shiftedfromrighttoleftonthenextCLKQuiz4. A4-bitparallel-in/parallel-outshiftregisterwillstoredatafor a.1clockperiod b.2clockperiods c.3clockperiods

d.4clockperiods5.The74HC164(shown)hastwoserialinputs.IfdataisplacedontheAinput,theBinput a.couldserveasanactiveLOWenable b.couldserveasanactiveHIGHenable c.shouldbeconnectedtoground d.shouldbeleftopenQuizCLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsABQuiz6. Apossiblesequencefora4-bitringcounteris a.…1111,1110,1101…

b.…0000,0001,0010… c.…0001,0011,0111…

d.…1000,0100,0010…Quiz7. AnadvantageofaringcounteroveraJohnsoncounteristhattheringcounter a.hasmorepossiblestatesforagivennumberofflip-flops b.isclearedaftereachcycle c.allowsonlyonebittochangeatatim