TFT-LCD-驱动原理与系统

TFTLCD驅動原理與系統TFTLCD驅動原理與系統液晶及液晶顯示器簡介TFTLCD驅動原理影響TFTLCD畫面品質的因素TFTLCDDriverICLCD數位界面簡介背光板簡介未來趨勢與走向被動式/主動矩陣式液晶顯示器Passive/ActiveMatrixLCDYelectrodeXelectrodePixelTheColorPixelofTFTLCDColorFilterSubstrateTFTSubstrateWhiteLightColorLightRGBBGRClcClcClcArrangementofColorFilterRGBRGBRGBRGBRGBRGBGRBG

RBGRBRBGRBGRBG

RGRG

GBGBRGRGGBGBRGRG

WBWBRGRGWBWBStripeTriangleGRBG

RBGRBGRBG

MosaicApertureRatioa-SiDrainelectrodeGateelectrodeInsulatorSourceelectroden+a-SiAdjacentgateelectrodeInsulator(dielectricsubstance)DisplayelectrodesTFTpixelEffectivearea:40.7%CapacitorTFTLCD驅動基本驅動波形極性反轉(polarityinversion)-Frame,row,column,dot電容耦合驅動-二階,三階,四階TimingChartofTFTLCDSFrameTimeTimeGate123N1HTFTLLCDSDrivingMethod

123451+++++2+++++3+++++4+++++5+++++

123451－－－－－2－－－－－3－－－－－4－－－－－5－－－－－

123451+++++2－－－－－3+++++4－－－－－5+++++

123451－－－－－2+++++3－－－－－4+++++5－－－－－

123451+－+－+2+－+－+3+－+－+4+－+－+5+－+－+

123451－+－+－2－+－+－3－+－+－4－+－+－5－+－+－

123451+－+－+2－+－+－3+－+－+4－+－+－5+－+－+

123451－+－+－2+－+－+3－+－+－4+－+－+5－+－+－FrameNColumnsFrameN+1ColumnsFrameNColumnsFrameN+1ColumnsColumnInversionDotInversionFrameNColumnsFrameN+1ColumnsFrameNColumnsFrameN+1ColumnsFrameInversionRowInversionDirectDrivingofTFTLCDsDCBiasofCommon1Frame/1LineGaryScalVoltageV63V62........V1V0V0V1........V62V63VcomAcModulation

AddressingofTFTLCDs1Frame/1LineCommonWaveformGraylevelVoltageV0V0V1V1V2V2V63V62V62V63DirectDrivingVs

VcomModulation

DirectDriving

－Frame,Row,Column&pixelinversionavailable－Cancelcrosstalk&removeflicker：imagequality－ImprovePowerdissipation

VcomModulation

－AvailableFrame&Rowinversion－PoorPowerdissipation影響LCD畫面品質的因素HorizontalCrosstalkVerticalCrosstalkShadingCrosstalk液晶電容的效應液晶電容CLC會隨液晶作用電壓的改變而變化，因此在驅動液晶時會有殘存的DC成份，其所造成的影響ImageSticking.PictureFlicker.液晶作用電壓大時，液晶分子趨向平行電場方向排列液晶作用電場小時，液晶分子趨向垂直電場方向排列Vp=Vgd－Vgd＝CgdVghlCgd+Cs+C－CgdVghlCgd+Cs+C⊥⊥HorizontalLineCrosstalkRGBCscCscCscColorFilterSubstrateBASignalofALineSignalofBLineCommonWaveformDifferenceofEffectiveVoltageinBLineBlackLevelGrayLevelGrayLevelHorizontalAreaCrosstalkBASignalofALineSignalofBLineCommonWaveformV1<V2V1V2DifferenceofEffectiveVoltageinBLineTFTLCDDriverICScan(gate,row)driverData(source,column)driverHighvoltage,mixedmodeUsuallyTCPpackageVendors：TIJapan,sharp,NEC,Toshiba,Matsushita,Hitachi,Samsung,LG,vivid,Winbond(cirruslogic,vivid),Mosel(sharp)…Maybeinthefuture,driverICisnotnecessaryinLargesizeLCDTheBlockDiagramoftheTFTLCDModuleTFT-LCDPANELCCFLBacklightDataDriverScanDriverTimingControllerRGBCLKHsxVsxTFTLCDModuleVideoSignalTimingSpec.ADECBHorizontalDisplayAreaHsTotalDisplayAreaOPQRSVerticalDisplayAreaVsTFT-LCDModuleControllerNO.1NO.4256256

ColorTFT-LCDPanel 1280x3x1024RGBNO.1NO.9NO.10

384

384

384ControlSignals(CPV,DI01,V1,V2)GMA0~GMA9ControlSignals(CLK,EI01…)DisplayData36(6bitsx3x2)VideoSignalTimingSpec.ModeVGASVGAXGASXGAUXGATotal800x5251056x6281344x8061688x10662160x1250Active640x480800x6001024x7681280x10241600x1200PixelClock25.175MHz40.000MHz65.000MHz108.000MHz162.000MHzFh31.469kHz37.879kHz48.363kHz63.981kHz75.000KHzFv59.941Hz60.317Hz60.004Hz60.020Hz60.000HzHTotal(A)31.78µs26.40µs20.68µs15.630µs13.333µsHDisplay(D)25.42µs20.00µs15.75µs11.852µs9.877µsVTotal(O)16.68ms16.58ms16.67ms16.661ms16.667msVDisplay(R)15.25ms15.84ms15.88ms16.005ms16.000msHsPolarity－＋－＋＋VsPolarity－＋－＋＋ResolutionVsOutputs-1FormatLines6543VGA480120SVGA600120150200XGA768128154192256SXGA1024256UXGA1200240GateDriverNo.ofDriversandNo.ofOutputChannelsChannels：120,120/128,150/154,192/200,240,256ResolutionVsOutputs-2FormatLines1210865VGA640*RGB192240384SVGA800*RGB240300402XGA1024*RGB309,312384SXGA1280*RGB384480UXGA1600*RGB402480SourceDriverNo.ofDriversandNo.ofOutputChannelsChannels：192/240,300/309,384,384/402ResolutionVsFmaxFrameRate60Hz70Hz75HzPixelFrequencyHorizontalPeriodPixelFrequencyHorizontalPeriodPixelFrequencyHorizontalPeriodVGA25.2MHz31.7µs31.5MHz26.7µsSVGA40MHz26.4µs49.5MHz21.3µsXGA65MHz20.7µs75MHz17.7µs78.75MHz16.7µsSXGA108MHz15.6µs135MHz12.5µsUXGA162MHz13.3µs189MHz11.4µs202.5MHz10.7µs解析度愈高，充電時間更短，DriverIC的Fmax也要愈快DataDriverKeySpecificationsChannelnumberGrayScale(6bits,8bit…)MaxOperationFreq.(45MHz,55MHz,65MHz…)PixelChargingTime(eg.R=2K,C=20pF,6.5µs90%,11.5µs100%)Lineorcolumn/dotinversionOutputvoltagedeviation(±10mV,±5mV,±3mV…)OperationvoltageDigital：5V,3.3V,2.5VAnalog：10V~15VOthers(datainversion,low-powermode,offsetcanceling,RSDS/LVDSinput…etc)DriverICTrend~240~300/309~384/402~480~65um~40um~50um40~55MHz~65MHz~85MHz3V/5V10V/15V3V/5V/10VLineInversionDotInversionLine/DotInversion6bit(64grayscale)8bit(256grayscale)2LevelGateDriver3LevelGateDriver’94’95’96’97’98’98‘2000UXGA1600x1200SXGA1280x1024XGA1024x768SVGA800x600VGA640x480DisplayResolutionTrendGrayScaleGrayScaleDrivingMethodOutputVoltageOperationFrequencyTCPILBPitchOutputChannelGateDataDriverICSpecLCD數位界面簡介類比PC界面簡介LCD數位界面簡介LVDSTMDSGVIFAnalogInterface

&TFTLCDModuleGraphicsControllerOSDADCBufferControllerPLLAnalogRGBHsVsDigitalRGBHsVsCLKHsxVsxTimingControllerScanDriverTFT-LCDPANELDigitalDataDriverCCFLBacklightPC ACDModule TFTLCDModuleDigitalInterface&

TFTLCDModuleLVDS/PanelLink

RxDigitalRGBClockHsVsTimingControllerScanDriverTFT-LCDPANELDigitalDataDriverCCFLBacklightGraphicsControllerLVDS/PanelLink

TxDigitalRGBClockHsVsPCCABLETFT-LCDModuleDigitalInterfaceHighimagequalityLongtransmissiondistanceSimplehardwareHighspeed,EMIproblemADC/DACnotneededTransmitter/receiverneededMaintechnologyLVDS,TMDS,GVIFStandardOpenLDI,DFP,DVI,DISM,…..TheDigitalInterface--LVDSLVDSinterface(TI,NS,Thine)LowvoltagedifferentialsignalingMainstreaminthenotebookPCnow(closesystem)7xinternalclockPLLrange：VGA(20mhz)toXGA(65mhz)Lowvoltageswings(0.250mv0.345mv0.450mv) ReducingEMI&highedgesharpnessimageNumberofcableline：4,5,9pairsLongdistancetransmission(5m)LVDSDevicePinNameSignalTxCLKIN/RxCLKOUTDotClockTxIN0/RxOUT0R0TxIN1/RxOUT1R1TxIN2/RxOUT2R2TxIN3/RxOUT3R3TxIN4/RxOUT4R4TxIN5/RxOUT5R7TxIN6/RxOUT6R5TxIN7/RxOUT7G0TxIN8/RxOUT8G1TxIN9/RxOUT9G2TxIN10/RxOUT10G6TxIN11/RxOUT11G7TxIN12/RxOUT12G3TxIN13/RxOUT13G4TxIN14/RxOUT14G5TxIN15/RxOUT15B0TxIN16/RxOUT16B6TxIN17/RxOUT17B7TxIN18/RxOUT18B1TxIN19/RxOUT19B2TxIN20/RxOUT20B3TxIN21/RxOUT21B4TxIN22/RxOUT22B5TxIN23/RxOUT23RESTxIN24/RxOUT24HSYNCTxIN25/RxOUT25VSYNCTxIN26/RxOUT26DETxIN27/RxOUT27R6TxCLKOUTRxCLKINTxOUT3/RxIN3TxOUT2/RxIN2TxOUT1/RxIN1TxOUT0/RxIN0PreviousCycleNextCycleTxIN5-1TxIN27-1TxIN23TxIN17TxIN16TxIN11TxIN10TxIN5TxIN27TxIN20-1TxIN19-1TxIN26TxIN25TxIN24TxIN22TxIN21TxIN20TxIN19TxIN9-1TxIN8-1TxIN18TxIN15TxIN14TxIN13TxIN12TxIN9TxIN8TxIN1-1TxIN0-1TxIN7TxIN6TxIN4TxIN3TxIN2TxIN1TxIN0FIGURE16.ParallelTTLDataInputsMappedtoLVDSOutputs(DS90CR583)LVDSHostGraphicsControllerLCDPanelControllerTxCLKINRxCLKOUTCmos/TTLCmos/TTLFPDLinkDS90CR583FPDLinkDS90CR584Data(LVDS)Clock(LVDS)ApplicationOpenLDITTLPARALLEL-TO-LVDSDCBALANCEDCBALANCE&DESKEWLVDS-TO-TTLPARALLELPLL888888888888RED1GRN1BLUE1RED2GRN2BLUE2RED1GRN1BLUE1RED2GRN2BLUE2FPLINEFPFRAMEDRDYControlFPSHIFTIN32.5–112MHz(170MHzSPM)CMOS/TTLInputsDS90C387DS90C387PLLLVDSDATA195–672MbpsperchannelLVDSCLOCK(32.5to112MHz)5.376GbpsFPLINEFPFRAMEDRDYControlFPSHIFTOUT32.5–112MHzCMOS/TTLInputsTheDigitalInterface--TMDSPanelLinkinterface(siliconimage)TransitionminimizeddifferentialsignalingAdoptedbytheLCDmonitorinterface(opensystem), Anddeterminethecorrectsamplingpoint.10xinternalclock&voltageswing=400to600mVOnly4twistedpairs,supportVGAtoUXGA3timesOversamplingtheserialdatastreamCodeisencodedtoprovideDCbalancingLongdistancetransmissioneasy(>5m)Data-to-dataskewtolerance1clockcycleTMDSTMDS(TransitionMinimizedDifferentialSignaling)isaninterfacestandardbasedonPanelLinkTechnologydevelopedbySiliconImage,Inc.SwingControlEncoder/SerializedPLLGraphicControllerTerminationControlRecovery/Decorder/DesirializerPLLLCDPanelDataDataDEDEControlsControlsClockClockTX1(Green)TX0(Blue)TX2(Red)Clock24524/365VCCVCCParallelData(CMOS)ParallelData(CMOS)TMDSI/FHostMonitorBlockDiagramofTNDSDVIDVI(digitalvisualinterface)PromotedbyDDWGIntel,IBM,HP,Compaq,NEC,Fujitsu,siliconimageDualchannelTMDSSupportVGAtoQXGAPixelclock：25mhz~330