文稿教案tca9548a模块

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ZHCSA11E–MAY2012–REVISEDOCTOBER81TCA9548ARON1.65V0400kHz–±2000V放电模式(A114-

TCA9548A器件配有八个可通过I2C总线控制的双向展为8个下行对或通道。根据可编程控制寄存器的内容，可选择任一单独SCn/SDn通道或者通道组合。RESETTCA9548A。同样，加电复位即可取消选中所有通道并初始化I2C/SMBus状TCA9548A的最大高电压。限制最大高电压允许在每3.3V部件可以在没有任何额外保护的情况下与5V部拉至所需的电压水平。所有I/O引脚为5V耐压。器件型封封装尺寸（标称值TSSOP7.80mm×VQFN4.00mmx要了解所有可用封装，请见数据表末尾的可订购产品附录SlavesH,SlavesSlavesB,SlavesA,AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,inlectualpropertymattersandotherimportantdiers.PRODUCTIONDATA.EnglishDataSheet:特 应用范 说 PinConfigurationand Absoluteum ESD mendedOperating Thermal Electrical I2CInterfaceTiming Switching ResetTiming Typical ParameterMeasurement Detailed

FunctionalBlock Feature DeviceFunctional Applicationand Application Typical Power Power-OnReset Layout Layout 社区资 商 静电放 ChangesfromRevisionD(January2015)toRevision UpdatedPinFunctions AddednewI2CSectionsandread/write ChangesfromRevisionC(November2013)toRevision UpdatedTypicalApplication ChangesfromRevisionB(November2013)toRevision UpdatedVPORandICCstandby ChangesfromRevisionA(July2012)toRevision PinConfigurationandPWPackageTop1234123456

24-PinVQFN

24232423222141011PinTSSOPQFN1Addressinput0.ConnectdirectlytoVCCor2Addressinput1.ConnectdirectlytoVCCor3Active-lowresetinput.ConnecttoVCCorVDPUM(1)throughapull-upresistor,ifnotused.41Serialdata0.ConnecttoVDPU0(1)throughapull-up52Serialclock0.ConnecttoVDPU0(1)throughapull-up63Serialdata1.ConnecttoVDPU1(1)throughapull-up74Serialclock1.ConnecttoVDPU1(1)throughapull-up85Serialdata2.ConnecttoVDPU2(1)throughapull-up96Serialclock2.ConnecttoVDPU2(1)throughapull-up7Serialdata3.ConnecttoVDPU3(1)throughapull-up8Serialclock3.ConnecttoVDPU3(1)throughapull-up9Serialdata4.ConnecttoVDPU4(1)throughapull-upSerialclock4.ConnecttoVDPU4(1)throughapull-upSerialdata5.ConnecttoVDPU5(1)throughapull-upSerialclock5.ConnecttoVDPU5(1)throughapull-upSerialdata6.ConnecttoVDPU6(1)throughapull-upSerialclock6.ConnecttoVDPU6(1)throughapull-upSerialdata7.ConnecttoVDPU7(1)throughapull-upSerialclock7.ConnecttoVDPU7(1)throughapull-upAddressinput2.ConnectdirectlytoVCCorSerialclockbus.ConnecttoVDPUM(1)throughapull-upSerialdatabus.ConnecttoVDPUM(1)throughapull-upSupply(1)VDPUXisthepull-upreferencevoltagefortheassociateddataline.VDPUMisthemasterI2CreferencevoltageandVDPU0-VDPU7aretheslavechannelreferencevoltages.Absoluteumoveroperatingfree-airtemperaturerange(unlessotherwiseSupply7VInput7VInputOutputSupplyStorageStressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder mendedOperatingConditionsisnotimplied.Exposuretoabsolute-um-ratedconditionsforextendedperiodsmayaffectdevicereliability.Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareESD Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-VCharged-devicemodel(CDM),perJEDECspecificationJESD22- JEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrol JEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolmendedOperatingSupplyVHigh-levelinputSCL,0.7×6VA2–A0,0.7×VCC+Low-levelinputSCL,0.3×VA2–A0,0.3×Operatingfree-airThermalTHERMALPWRGE2424Junction-to-ambientthermalJunction-to-case(top)thermalJunction-to-boardthermalJunction-to-topcharacterizationJunction-to-boardcharacterizationJunction-to-case(bottom)thermal(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,ElectricalVCC=2.3Vto3.6V, mendedoperatingfree-airtemperaturerange(unlessotherwiseTESTPower-onresetvoltage,VCCNoload,VI=VCCorVPower-onresetvoltage,VCCNoload,VI=VCCor VSwitchoutputVi(sw)=VCC,ISWout=–1005V4.5Vto5.53.33VtoVto2.7 1.81.65Vto1.95VOL=0.41.65Vto5.536VOL=0.669SCL,VI=VCCor1.65Vto5.51SC7–SC0,111OperatingfSCL=400VI=VCCorGND(3),IO=1.656fSCL=100VI=VCCorGND(3),IO=5.593.662.7481.6524StandbyLowVI=GND(3),IO=5.5 3.6 2.7 1.65 HighVI=VCC,IO=5.5 3.6 2.7 1.65 SCL,SCLorSDAinputat0.6V,OtherinputsatVCCorGND(3)1.65Vto5.53SCLorSDAinputatVCC–0.6V,OtherinputsatVCCorGND(3)3VI=VCCor1.65Vto5.54545VI=VCCorGND(3),SwitchCio(off)VI=VCCorGND(3),Switch1.65Vto5.5SC7–SC0,Foroperationbetweenspecifiedvoltageranges,refertotheworst-caseparameterinbothapplicableAlltypicalvaluesareatnominalsupplyvoltage(1.8-V,2.5-V,3.3-V,or5-VVCC),TA=RESET=VCC(heldhigh)whenallotherinputvoltages,VI=Thepower-onresetcircuitresetstheI2CbuslogicwithVCC<Cio(ON)dependsoninternalcapacitanceandexternalcapacitanceaddedtotheSCnlineswhenchannels(s)areElectricalCharacteristics(1)VCC=2.3Vto3.6V, mendedoperatingfree-airtemperaturerange(unlessotherwiseTESTSwitch-onVO=0.4V,IO=154.5Vto5.54Ω3Vto3.65VO=0.4V,IO=102.3Vto2.771.65Vto1.95I2CInterfaceTiming mendedoperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigureI2CBUSI2CBUSI2Cclock00I2Cclockhigh4I2CclocklowI2CeI2Cserial-datasetupI2Cserial-dataholdI2Cinputrise20+0.1CbI2Cinputfall20+0.1CbI2Coutput(SDn)falltime(10-pFto400-pF20+0.1CbI2CbusfreetimebetweenstopandI2CstartorrepeatedstartconditionI2Cstartorrepeatedstartcondition4I2Cstopcondition4Valid-datatime(hightoSCLlowtoSDAoutputlow11Valid-datatime(lowtoSCLlowtoSDAoutputhighValid-datatimeofACKACKsignalfromSCLlowtoSDAoutputlow11I2CbuscapacitiveAdeviceinternallymustprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheVIHminoftheSCLsignal),tobridgetheundefinedregionofthefallingedgeofSCL.Cb=totalbuscapacitanceofonebuslineinDatatakenusinga1-kΩpull-upresistorand50-pFload(seeFigureSwitching mendedoperatingfree-airtemperaturerange,CL≤100pF(unlessotherwisenoted)(seeFigure tpd PropagationdelayRON=20Ω,CL=15SDAorSDnorRON=20Ω,CL=501trst RESETtime(SDAThepropagationdelayisthecalculatedRCtimeconstantofthetypicalON-stateoftheswitchandthespecifiedloadcapacitance,whendrivenbyanidealvoltagesource(zerooutputimpedance).trstisthepropagationdelaymeasuredfromthetimetheRESETpinisfirstassertedlowtothetimetheSDApinisassertedhigh,signalingastopcondition.ItmustbeaminimumoftWL.CIO(OFF)CIO(OFF)RON(!ResetTiming mendedoperatingfree-airtemperaturerange(unlessotherwise Pulseduration,RESET6 RecoverytimefromRESETto0VCC=5.5VVVCC=5.5VVCC=3.3VVCC= 125ºC(RoomTemperature)-00246IOL8 VCC Figure1.SDAOutputLowVoltage(VOL)vsLoadCurrent(IOL)atThreeVCCLevels625ºC(RoomFigure2.StandbyCurrent(ICC)vsSupplyVoltage(VCC)atThreeTemperaturePoints- 54525ºC(RoomTemperature)-0 VCC VCCFigure3.SlaveChannel(SCn/SDn)Capacitance(Cio(OFF))SupplyVoltage(VCC)atThreeTemperatureFigure4.(RON)vsSupplyVoltage(VCC)atThreeTemperaturesVOLICC,StandbyModeParameterMeasurementR=1C=50(seeNoteSDALOADCondition BitCondition Bit AddressBitBit1BitBit1Bit0Bit7 Bit0

0.3ttStart

RepeatStart

VOLTAGE

1IC2,P-portCLincludesprobeandjigAllinputsaredbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,ZO=50Ω,tr/tf≤30NotallparametersandwaveformsareapplicabletoallFigure5.I2CLoadCircuitandVoltageParameterMeasurementInformationRL=1CL=50(seeNoteSDALOADACKACKorRead

0.3VCCSDn,CLincludesprobeandjig

Allinputsaredbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,ZO=50Ω,tr/tf≤30I/OsareconfiguredasNotallparametersandwaveformsareapplicabletoallFigure6.ResetLoadCircuitandVoltageDetailedTheTCA9548Aisan8-channel,bidirectionaltranslatingI2Cswitch.ThemasterSCL/SDAsignalpairisdirectedtoeightchannelsofslavedevices,SC0/SD0-SC7/SD7.Anyindividualdownstreamchannelcanbeselectedaswellasanycombinationoftheeightchannels.Thedeviceoffersanactive-lowRESETinputwhichresetsthestatemachineandallowstheTCA9548AtorecovershouldoneofthedownstreamI2Cbusesgetstuckinalowstate.Thestatemachineofthedevicecanalsoberesetbycyclingthepowersupply,VCC,alsoknownasapower-onreset(POR).BoththeRESETfunctionandaPORwillcauseallchannelstobedeselected.TheconnectionsoftheI2CdatapatharecontrolledbythesameI2CmasterdevicethatisswitchedtocommunicatewithmultipleI2Cslaves.Afterthesuccessfulacknowledgmentoftheslaveaddress(hardwareselectablebyA0,A1,andA2pins),asingle8-bitcontrolregisteriswrittentoorreadfromtodeterminetheselectedchannels.TheTCA9548Amayalsobeusedforvoltagetranslation,allowingtheuseofdifferentbusvoltagesoneachSCn/SDnpairsuchthat1.8-V,2.5-V,or3.3-Vpartscancommunicatewith5-Vparts.Thisisachievedbyusingexternalpull-upresistorstopullthebusuptothedesiredvoltageforthemasterandeachslavechannel.FunctionalBlock57957946SwitchControl3Reset1InputICBus2 FeatureTheTCA9548Aisan8-channel,bidirectionaltranslatingswitchforI2CbusesthatsupportsStandard-Mode(100kHz)andFast-Mode(400kHz)operation.TheTCA9548AfeaturesI2Ccontrolusingasingle8-bitcontrolregisterinwhicheachbitcontrolstheenablinganddisablingofoneofthecorresponding8switchchannelsforI2Cdataflow.Dependingontheapplication,voltagetranslationoftheI2CbuscanalsobeachievedusingtheTCA9548Atoallow1.8-V,2.5-V,or3.3-Vpartstocommunicatewith5-Vparts.Additionally,intheeventthatcommunicationontheI2Cbusentersafaultstate,theTCA9548AcanberesettoresumenormaloperationusingtheRESETpinfeatureorbyapower-onresetwhichresultsfromcyclingpowertothedevice.DeviceFunctionalRESETTheRESETinputisanactive-lowsignalthatmaybeusedtorecoverfromabus-faultcondition.WhenthissignalisassertedlowforaminimumoftWL,theTCA9548AresetsitsregistersandI2Cstatemachineanddeselectsallchannels.TheRESETinputmustbeconnectedtoVCCthroughapull-upresistor.WhenpowerisappliedtotheVCCpin,aninternalpower-onresetholdstheTCA9548AinaresetconditionuntilVCChasreachedVPORR.Atthispoint,theresetconditionisreleased,andtheTCA9548AregistersandI2Cstatemachineareinitializedtotheirdefaultstates,allzeroes,causingallthechannelstobedeselected.Thereafter,VCCmustbeloweredbelowVPORFtoresetthedevice.I2CTheTCA9548AhasastandardbidirectionalI2Cinterfacethatiscontrolledbyamasterdeviceinordertobeconfiguredorreadthestatusofthisdevice.EachslaveontheI2CbushasaspecificdeviceaddresstodifferentiatebetweenotherslavedevicesthatareonthesameI2Cbus.Manyslavedeviceswillrequireconfigurationuponstartuptosetthebehaviorofthedevice.Thisistypicallydonewhenthemasteraccessesinternalregistermapsoftheslave,whichhaveuniqueregisteraddresses.Adevicecanhaveoneormultipleregisterswheredataisstored,written,orread.ThephysicalI2Cinterfaceconsistsoftheserialclock(SCL)andserialdata(SDA)lines.BothSDAandSCLlinesmustbeconnectedtoVCCthroughapull-upresistor.Thesizeofthepull-upresistorisdeterminedbytheamountofcapacitanceontheI2Clines.(Forfurtherdetails,refertoI2CPull-upResistorCalculation(SLVA689).)Datatransfermaybeinitiatedonlywhenthebusisidle.AbusisconsideredidleifbothSDAandSCLlinesarehighafteraSTOPcondition.ThefollowingisthegeneralprocedureforamastertoaccessaslaveIfamasterwantstosenddatatoaMaster-transmittersendsaSTARTconditionandaddressestheslave-Master-transmittersendsdatatoslave-Master-transmitterterminatesthetransferwithaSTOPIfamasterwantstoreceiveorreaddatafromaMaster-receiversendsaSTARTconditionandaddressestheslave-Master-receiversendstherequestedregistertoreadtoslave-Master-receiverreceivesdatafromtheslave-Master-receiverterminatesthetransferwithaSTOP

DataTransfer Figure7.DefinitionofStartandStopSDAlinestablewhileSCLlineis1010101010 Byte:10101010(0xAAhFigure8.BitDeviceFigure9showstheaddressbyteoftheSlave1110 Figure9.TCA9548AThelastbitoftheslaveaddressdefinestheoperation(readorwrite)tobeperformed.Whenitishigh(1),areadisselected,whilealow(0)selectsawriteoperation.Table1.AddressI2CBUSSLAVELLL112(decimal),70LLH113(decimal),71LHL114(decimal),72LHH115(decimal),73HLL116(decimal),74HLH117(decimal),75HHL118(decimal),76HHH119(decimal),77BusDatamustbesenttoandreceivedfromtheslavedevices,andthisis plishedbyreadingfromorwritingtoregistersintheslavedevice.Registersarelocationsinthememoryoftheslavewhichcontaininformation,whetheritbetheconfigurationinformationorsomesampleddatatosendbacktothemaster.Themastermustwriteinformationtotheseregistersinordertoinstructtheslavedevicetoperformatask.WhileitiscommontohaveregistersinI2Cslaves,notethatnotallslavedeviceswillhaveregisters.Somedevicesaresimpleandcontainonly1register,whichmaybewrittentodirectlybysendingtheregisterdataimmediayaftertheslaveaddress,insteadofaddressingaregister.TheTCA9548Aisexampleofasingle-registerdevice,whichiscontrolledviaI2Ccommands.Sinceithas1bittoenableordisableachannel,thereisonly1registerneeded,andthemastermerelywritestheregisterdataaftertheslaveaddress,skiptheregisternumber.TowriteontheI2Cbus,themasterwillsendaSTARTconditiononthebuswiththeaddressoftheslave,aswellasthelastbit(theR/Wbit)setto0,whichsignifiesawrite.Theslavewillacknowledge,lettingthemasterknowitisready.Afterthis,themasterwillstartsendingthecontrolregisterdatatotheslaveuntilthemasterhassentallthedatanecessary(whichissometimesonlyasinglebyte),andthemasterwillterminatethetransmissionwithaSTOPcondition.Thereisnolimittothenumberofbytessent,butthelastbytesentiswhatwillbeintheregister.Figure10showsanexampleofwritingasinglebytetoaslaveregister.MastercontrolsSDAlineSlavecontrolsSDAlineWritetooneregisterinaDevice(Slave)Address(7 ControlRegister(8S11100AAP ACKFigure10.WritetoReadingfromaslaveisverysimilartowriting,butthemasterwillsendaSTARTcondition,followedbytheslaveaddresswiththeR/Wbitsetto1(signifyingaread).Theslavewillacknowledgethereadrequest,andthemasterwillreleasetheSDAbusbutwillcontinuesupplyingtheclocktotheslave.Duringthispartofthetransaction,themasterwill ethemaster-receiver,andtheslavewill etheslave-transmitter.Themasterwillcontinuetosendouttheclockpulses,butwillreleasetheSDAlinesothattheslavecantransmitdata.Attheendofeverybyteofdata,themasterwillsendanACKtotheslave,lettingtheslaveknowthatitisreadyformoredata.Oncethemasterhasreceivedthenumberofbytesitisexpecting,itwillsendaNACK,signalingtotheslavetohaltcommunicationsandreleasethebus.ThemasterwillfollowthisupwithaSTOPFigure11showsanexampleofreadingasinglebytefromaslaveMastercontrolsSDAlineSlavecontrolsSDAlineDevice(Slave)Address(7 ControlRegister(8S11101AP NACKFigure11.ReadfromControlControlFollowingthesuccessfulacknowledgmentoftheaddressbyte,thebusmastersendsacommandbytethatisstoredinthecontrolregisterintheTCA9548A(seeFigure12).ThisregistercanbewrittenandreadviatheI2Cbus.EachbitinthecommandbytecorrespondstoaSCn/SDnchannelandahigh(or1)selectsthischannel.MultipleSCn/SDnchannelsmaybeselectedatthesametime.Whenachannelisselected,thechannelesactiveafterastopconditionhasbeenplacedontheI2Cbus.ThisensuresthatallSCn/SDnlinesareinahighstatewhenthechannelismadeactive,sothatnofalseconditionsaregeneratedatthetimeofconnection.Astopconditionalwaysmustoccurimmediayaftertheacknowledgecycle.IfmultiplebytesarereceivedbytheTCA9548A,itsavesthelastbytereceived.ChannelChannelChannelChannelChannelChannelChannelFigure12.Control

ChannelTable2.CommandByteCONTROLREGISTERXXXXXXX0Channel01Channel0XXXXXX0XChannel11Channel1XXXXX0XXChannel21Channel2XXXX0XXXChannel31Channel3XXX0XXXXChannel41Channel4XX0XXXXXChannel51Channel5X0XXXXXXChannel61Channel60XXXXXXXChannel71Channel700000000Nochannelselected,power-up/resetdefaultstateRESETTheRESETinputisanactive-lowsignalthatmaybeusedtorecoverfromabus-faultcondition.WhenthissignalisassertedlowforaminimumoftWL,theTCA9548AresetsitsregistersandI2Cstatemachineanddeselectsallchannels.TheRESETinputmustbeconnectedtoVCCthroughapull-upresistor.Whenpower(from0V)isappliedtoVCC,aninternalpower-onresetholdstheTCA9548AinaresetconditionuntilVCChasreachedVPOR.Atthatpoint,theresetconditionisreleasedandtheTCA9548AregistersandI2Cstatemachineinitializetotheirdefaultstates.Afterthat,VCCmustbeloweredtobelowVPORandthenbackuptotheoperatingvoltageforapower-resetcycle.ApplicationandInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.TI’scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.ApplicationApplicationsoftheTCA9548AwillcontainanI2C(orSMBus)masterdeviceanduptoeightI2Cslavedevices.ThedownstreamchannelsareideallyusedtoresolveI2Cslaveaddress s.Forexample,ifeightidenticaldigitaltemperaturesensorsareneededintheapplication,onesensorcanbeconnectedateachchannel:0-7.Whenthetemperatureataspecificlocationneedstoberead,theappropriatechannelcanbeenabledandallotherchannelsswitchedoff,thedatacanberetrieved,andtheI2CmastercanmoveonandreadthenextInanapplicationwheretheI2CbuswillcontainmanyadditionalslavedevicesthatdonotresultinI2Cslave s,theseslavedevicescanbeconnectedtoanydesiredchanneltodistributethetotalbuscapacitanceacrossmultiplechannels.Ifmultipleswitcheswillbeenabledsimultaneously,additionaldesignrequirementsmustbeconsidered(seeDesignRequirementsandDetailedDesignProcedure).TypicalFigure13showsanapplicationinwhichtheTCA9548AcanbeTypicalTypicalApplicationVDPUM=1.65Vto5.5

SD0

VDPU0=1.65Vto5.5

22

SC0

Channel0VDPU1=1.65Vto5.5VSD1SC1

VDPU2=1.65Vto5.5SD2SC2

VDPU3=1.65Vto5.5

Channel3VDPU4=1.65Vto5.5 4VDPU5=1.65Vto5.5SD5SC5

VDPU6=1.65Vto5.5212112

SD6SC6SC7

Channel6VDPU7=1.65Vto5.5V PinnumbersshownareforthePWFigure13.TypicalApplicationDesignAtypicalapplicationoftheTCA9548Awillcontainoneormoredatapull-upvoltages,VDPUX,oneforthemasterdevice(VDPUM)andoneforeachoftheselectableslavechannels(VDPU0–VDPU7).Intheeventwherethemasterdeviceandallslavedevicesoperateatthesamevoltage,thenVDPUM=VDPUX=VCC.Inanapplicationwherevoltagetranslationisnecessary,additionaldesignrequirementsmustbeconsideredtodetermineanappropriateVCCvoltage.TheA0,A1,andA2pinsarehardwareselectabletocontroltheslaveaddressoftheTCA9548A.ThesepinsmaybetieddirectlytoGNDorVCCintheapplication.Ifmultipleslavechannelswillbeactivatedsimultaneouslyintheapplication,thenthetotalIOLfromSCL/SDAtoGNDonthemastersidewillbethesumofthecurrentsthroughallpull-upresistors,Rp.Thepass-gatetransistorsoftheTCA9548AareconstructedsuchthattheVCCvoltagecanbeusedtolimittheumvoltagethatispassedfromoneI2Cbustoanother.Figure14showsthevoltagecharacteristicsofthepass-gatetransistors(notethatthegraphwasgeneratedusingdataspecifiedinElectricalCharacteristics).InorderfortheTCA9548Atoactasavoltagetranslator,theVpassvoltagemustbeequaltoorlowerthanthelowestbusvoltage.Forexample,ifthemainbusisrunningat5Vandthedownstreambusesare3.3Vand2.7V,Vpassmustbeequaltoorbelow2.7Vtoeffectivelyclampthedownstreambusvoltages.AsshowninFigure14,Vpass(max)is2.7VwhentheTCA9548Asupplyvoltageis4Vorlower,sotheTCA9548Asupplyvoltagecouldbesetto3.3V.Pull-upresistorsthencanbeusedtobringthebusvoltagestotheirappropriatelevels(seeFigure13).DetailedDesignOncealltheslavesareassignedtotheappropriateslavechannelsandbusvoltagesareidentified,thepull-upresistors,Rp,foreachofthebusesneedtobeselectedappropriay.Theminimumpull-upisafunctionofVDPUX,VOL,(max),andIOL:

VDPUX umpull-up isafunctionofthe umrisetime,tr(300nsforfast-modeoperation,fSCL=400kHz)andbuscapacitance,Cb:

0.8473 umbuscapacitanceforanI2Cbusmustnotexceed400pFforfast-modeoperation.ThebuscapacitancecanbeapproximatedbyaddingthecapacitanceoftheTCA9548A,Cio(OFF),thecapacitanceofwires/connections/traces,andthecapacitanceofeachindividualslaveonagivenchannel.Ifmultiplechannelswillbeactivatedsimultaneously,eachoftheslavesonallchannelswillcontributetototalbuscapacitance.5425ºC(RoomTemperature)-5425ºC(RoomTemperature)-3 VCC CbFast-(fSCL=400kHz,tr=300Standard-(fSCL=100kHz,tr=1Figure14.Pass-GateVoltage(Vpass)vsSupplyVoltage(VCC)atThreeTemperaturePointsFigureumPull-Up (Rp(max))vsBusCapacitance(Cb)1VDPUX>2VVDPUX<=0 VDPUXVOL=0.2*VDPUX,IOL=2mAwhenVDPUX≤2VVOL=0.4V,IOL=3mAwhenVDPUX>2VFigure16.Minimum(Rp(min))vsPullupReferenceVoltageVpassRp(min)Rp(max)Power Theoperatingpower-supplyvoltagerangeoftheTCA9548Ais1.65Vto5.5VappliedattheVCCpin.WhentheTCA9548Aispoweredonforthefirsttimeoranytimethedevicemustberesetbycyclingthepowersupply,thepower-onresetrequirementsmustbefollowedtoensuretheI2Cbuslogicisinitializedproperly.Power-OnResetIntheeventofaglitchordatacorruption,TCA9548Acanberesettoitsdefaultconditionsbyusingthepower-onresetfeature.Power-onresetrequiresthatthedevicegothroughapowercycletobecompleyreset.Thisresetalsohappenswhenthedeviceispoweredonforthefirsttimeinanapplication.Apower-onresetisshowninFigureVCCdropsVCCdropsbelowVPORF50RampVCCRampVCCTimetoReVCCVCCisLoweredBelowthePORThreshold,ThenRampedBackUptoFigure17.Power-OnResetTable3specifiestheperformanceofthepower-onresetfeatureforTCA9548Aforbothtypesofpower-onTable mendedSupplySequencingandRampFallFigure1RiseFigureTimetore-ramp(whenVCCdropsbelowVPORF(min)–50mVorwhenVCCdropstoGND)FigureLevelthatVCCcanglitchdownto,butnotcauseafunctionaldisruptionwhenVCC_GW=1μsFigureVGlitchwidththatwillnotcauseafunctionaldisruptionwhenVCC_GH=0.5×VCCFigure(1)AllsupplysequencingandrampratevaluesaremeasuredatTA=Glitchesinthepowersupplycanalsoaffectthepower-onresetperformanceofthisdevice.Theglitchwidth(VCC_GW)andheight(VCC_GH)aredependentoneachother.Thebypasscapacitance,sourceimpedance,anddeviceimpedancearefactorsthataffectpower-onresetperformance.Figure18andTable3providemoreinformationonhowtomeasurethesespecifications.VCCVCCVCCFigure18.GlitchWidthandGlitchVPORiscriticaltothepower-onreset.VPORisthevoltagelevelatwhichtheresetconditionisreleasedandalltheregistersandtheI2C/SMBusstatemachineareinitializedtotheirdefaultstates.ThevalueofVPORdiffersbasedontheVCCbeingloweredtoorfrom0.Figure19andTable3providemoredetailsonthisspecification.Figure19.LayoutForPCBlayoutoftheTCA9548A,commonPCBlayoutpracticesshouldbefollowedbutadditionalconcernsrelatedtohigh-speeddatatransfersuchasmatchedimpedancesanddifferentialpairsarenotaconcernforI2Csignalspeeds.Itiscommontohaveadedicatedgroundplaneonaninnerlayeroftheboardandpinsthatareconnectedtogroundshouldhavealow-impedancepathtothegroundplaneintheformofwidepolygonpoursandmultiplevias.By-passandde-couplingcapacitorsarecommonlyusedtocontrolthevoltageontheVCCpin,usingalargercapacitortoprovideadditionalpowerintheeventofashortpowersupplyglitchandasmallercapacitortofilterouthigh-frequencyripple.Inanapplicationwherevoltagetranslationisnotrequired,allVDPUXvoltagesandVCCcouldbeatthesamepotentialandasinglecopperplanecouldconnectallofpull-upresistorstotheappropriatereferencevoltage.Inanapplicationwherevoltagetranslationisrequired,VDPUMandVDPU0-VDPU7,mayallbeonthesamelayeroftheboardwithsplitplanestoisolatedifferentvoltagepotentials.ToreducethetotalI2CbuscapacitanceaddedbyPCBparasitics,datalines(SCnandSDn)shouldbeashortaspossibleandthewidthsofthetracesshouldalsobeminimized(e.g.5-10milsdependingoncopperweight).ToSlaveChannelToSlaveChannelToSlaveChannelToSlaveChannelToSlaveChannel(innerCopperToIC(outerViatoPowerViatoGND12RESET 56 9ToSlaveChannelToSlaveToSlaveChannelToSlaveChannelToSlaveChannelToSlaveChannelThefollowinglinksconnecttoTIcommunityresources.Linkedcontentsareprovided"ASIS"bytherespectivecontributors.TheydonotconstituteTIspecificationsanddo