液晶显示器驱动系统

1、主动矩阵式液晶显示器AM-LCDsTFT LCDs等效电路Row DriversColumn DriverArrangement of Color FilterR G B R G BR G B R G BR G B R G BRBG RGBRBGRBG RGBRBGRBG RGBRBGRGGBRGGBRGGBRGGBRGW BRGW BRGW BRGW BStripeTrianglePixel Structure of TFT LCDsClcCsClcCsCommonCommon (N-1)thScan Line (N-1)thScan LineNth Scan LineNth Scan Li

2、neCs on Common Mode Cs on Gate ModeCgdCgd液晶電容儲存電容掃描電極資料電極共通電極Mth Data LineMth Data Line資料電極掃描電極:Clc:Cs:Common:Cgd寄生電容液晶畫素電容:Clc+CsClcCsCommon1 (N-1)thScan LineNth Scan LineCs on Gate ModeCgdMth Data Line資料電極Common2Cs on Common与Cs on Gate架构液晶画素TFTGate LineData LineCsCs液晶画素TFTCommonCommonGate LineData

3、 LineCsCs Cs onCommonCs on GateTiming Chart of TFT LCDsFrame TimeGate123NTimeTFT LCDs Driving Method1 2 3 4 512345Frame NColumnsLines+ + + + + + + + + + + + + + + + + + + + +1 2 3 4 512345Frame N+1 ColumnsLines 1 2 3 4 512345Frame NColumnsLines+ + + + + + + + + + + + +1 2 3 4 512345Frame N+1 Columns

4、Lines + + + + + + + + + 1 2 3 4 512345Frame NColumnsLines+ + +1 2 3 4 512345Frame N+1 ColumnsLines + + + + + + + + + + + + + + + + + + + 1 2 3 4 512345Frame NColumnsLines+ + +1 2 3 4 512345Frame N+1 ColumnsLines+ + + + + + + + + + + + + + + + + + + +Column InversionDot InversionRow InversionFrame In

5、versionDirect Driving of TFT LCDs DC Biasof CommonGrayScale VoltageV0V1V2V3V4V5V6V7V7V6V5V4V3V2V1V01Frame / 1 LineAC Modulation Addressing of TFT LCDsV0V1V2V3V4V5V6V7V7V6V5V4V3V2V1V0Common WaveformGraylevel Voltage1Frame / 1 LineTFT LCDs的电光效应Direct AddressingT100%VVthVth:液晶的操作臨界電壓共通電極訊號位準正極性訊號時光電轉移曲

6、線負極性訊號時光電轉移曲線Vth負極性時臨界電壓正極性時臨界電壓5V3.5V6.5VTFT LCDs的电光效应AC AddressingT100%V5V-1.5VVthVth:液晶的操作臨界電壓 正極性訊號時共通電極訊號位準 負極性訊號時共通電極訊號位準正極性訊號時光電轉移曲線負極性訊號時光電轉移曲線VthTFT LCDs Driving Waveform Cs on Common (一)SourceDrainGateVgppVsppVgon-minVgoff-minVshVdhVslVdlVgdVghVglVgdCommonVstVst:影像訊號的直流位準TgTFT LCD驱动波形 (Cs

7、on Common, Common = DC Bias)TFT LCDs Driving Waveform Cs on Common (二)SourceDrainGateVgppVsppVgon-minVgoff-minVshVdhVslVdlVgdVghVglVctVstVgd Common WaveFormVcppTFT LCDs Driving Waveform Cs on GateSourceDrainGateVgppVsppVgon-minVgoff-minVshVdhVslVdlVgdVghVglVgdCommonVstVst:影像訊號的直流位準VdVdTgVc:TFT电容效应的影

8、响PixelCgdCgsCsdCsdbCsdbVVVVVVpFCpFCpFCExCCCVCCCCCVCVgdglghghlgdsLCLCsgdghlgdsdLCsgdghlgdgd43. 13005. 08 . 02 . 005. 030102005. 0,8 . 0,2 . 0:液晶电容的效应 液晶电容CLC 会随液晶作用电压的改变而变化，因此在驱动液晶时会有残存的DC成份，其所造成的影响： Image Sticking. Picture Flicker. 液晶作用电压大时，液晶分子趋向平行电场方向排列： 液晶作用电场小时，液晶分子趋向垂直电场方向排列：IIsgdghlgdsgdghlgdg

9、dgdpCCCVCCCCVCVVV/二阶驱动方式的效应CsClcCgdCsdCgsVctCh(N-1)Ch(N)Vs垂直影像讯号水平扫描讯号Vg水平扫描讯号VgVshVslVstVthVth正极性驱动负极性驱动负极性驱动正极性驱动数据驱动芯片输出讯号电位液晶画素电位Vct=Vst-VpVpBlack(+)White(+)White(+)Black(+)Black(-)Black(-)White(-)White(-)TFT补偿驱动法Ch(N-1)Ch(N)Vst=Vct影像讯号波形Vs水平脉波扫描波形VgeVgeVghlCh(N-1)Ch(N)Vst影像讯号波形VsVge(+)Vge(-)Vgh

10、lVghl sghlgdstgesghlgdstgeCVCCVCVCVCCVCV*sghlgdgeCVCV3Level Addressing4Level Addressing3Level AddressingB(+)W(-)B(-)W(+)正极性负极性Vst=VctB(+)B(-)W(+)W(-)B(+)W(-)B(-)W(+) Vp=CgdVghl/Ct正极性负极性正极性Ct=Cs+Clc+Cgd负极性CsVge/CtCsVge/Ct4Level AddressingVst=VctB(+)B(-)B(-)B(+)W(+)W(+)W(-)W(-)B(+)W(-)B(-)W(+)Vp(+)Vp(

11、-)Vp=CgdVghl/CtCsVge(-)/CtCsVge(+)/Ct正极性负极性正极性负极性Ct=Cs+Clc+CgdCs on Gate电压补偿方式经由Cs将前一条水平脉波的补偿波形耦合到动作的液晶画素, 补偿Cgd造成的电压漂移及改善液晶画素内的直流电电压残余.经由TFT的Cgd造成的电压漂移经由TFT的Cgd造成的电压漂移Comparsion of Addressing MethodFrameLineColumnDotCommonModulationModulationDCDCOutputRange ofDataLow VoltageLow VoltageHigh Voltage

12、High Voltage2-LevelDrivingVVVV3-LevelDrivingV(Note 1)V(Note 1)VV4-LevelDrivingVVXXV : 可使用 X : 不可使用Note 1: Common 必須採用 DC Mode 驅動表一 Driving MethodHorizontal Line CrosstalkGray LevelGray Level Black LevelCommon WaveformDifference of Effective Voltagein B LineSignal of A LineSignal of B LineABCscCscCsc

13、TFT SubstrateColor Filter SubstrateHorizontal Area CrosstalkCommon WaveformDifference of Effective Voltagein B LineSignal of A LineSignal of B LineV1V2V1V2ABVertical Area CrosstalkCsdCsdbCsdbPixelGate LineSource LineUpLowUpLowShading CrosstalkRgRgRgRgClcCsRgRgClcCsRgRgClcCsRsRsRsCgsCgsCgsIg*nIg*(n-1

14、)Ig*(n-2)IgIgIgIg*nIg*(n-1)Ig*(n-2)IcIcIcIc*nIc*(n-1)Ic*(n-2)Ic*(n-3)IsIsIsIgIgIgCruuent FromGate Driver N-1Current FromGate Driver N Common PlateCurrent From Common Plate Connection圖2.7a Line Inverion Charging PathShading Crosstalk的抑制RgRgRgRgClcCsRgRgClcCsRgRgClcCsRsRsRsCgsCgsCgsIgIgIgIcIcIcIsIsIsI

15、gIgIgGate Driver N-1Gate Driver N Common PlateIg/2Ig/2Ig/2Ig/2Ig/2Ig/2Ig/2Ig/2Ic/2Ic/2Ic/2Ic/2圖2.7b Column/Dot Inversion Charging PathGate Pulse的传递延迟Gate (Scan) Line的等效阻抗为一连串的串联 RC网络，因此 Gate Pulse在传递时会造成波形的传递延迟失真。RCRCRCRCNRCNeq22液晶画素边际电场效应(一)Reverse Tilt画素电极邻近电极共通电极VPVLVAVA VL : Disclination Disappe

16、aredVP LC Threshold VoltageReverse Tilt液晶画素边际电场效应(二)TFT水平驱动电极垂直驱动电极RubbingDirectionDisclinationLineReverse TiltDomain改善方法1.增加液晶分子的 预倾角(Pretilt Angle)2.增加Black Mask的 遮蔽面积驱动IC Scan DriverBidirectional Shift RegisterLevel Shift CircuitOutput BufferG1 G2 G3 .STVRSTVLCPVR/LVDDDVSSDVDDAVSSASTVRSTVLG1G2GxS

17、erial In Serial Out Analog Data DriverSelectData jData j+1MultiplexerPro:Very simple. Fewer external connections.Con:Many analog inputs. Reduced pixel charging time.System Note : Sample clock : (Dot clock) / N, N Phases. Video Phase : NShift RegisterVideo InQiQi+1Variation on MultiplexerPro:Video In

18、put.Con:Fast data line charging needed. Reduced pixel charging time.System Note: Shift Clock : (Dot Clock) / 3 for Mono. Video Phase : 3 for Mono.Sample and HoldSerial In Parallel OutAnalog Data Driver (一)Shift RegisterQiQi+1Qi+2Qi+3Video InTransferDouble Sample and Hold / Single PhaseSample NSample

19、 N+1Sample N+2TTTNN+1N+2Out N-1Out NOut N+1Pro:Video Input. Small load on fast sample-and-holds. Full line time to charge pixel.Con:Complex analog circuit. Physical size.System Note : Shift Clock : Dot Clock. Video Phase : Single Phase.Serial In Parallel OutAnalog Data Driver (二)Shift RegisterQiQi+1

20、Video InTransferDouble Sample and Hold / Multi-PhasePor : Reduced operation frequency .System Note :Video In : NVideo Phase : NShift Clock : (Dot Clock) / N.Digital Data Driver (一)Shift RegisterDACDACDACDACDAC SerialData BusDigital-to-analog ConvertersPor : Digital input.Con : Complex. Requires suff

21、icient precision to correct for LC response variation.Shift RegisterCount Count Count Count CountRamp InSampled RampPor : Digital input. Programmable ramp.Con : Complex circuit. High speed digital circuits. Reduced pixel charging time.Digital Data Driver (二)Shift RegisterDecodeDecodeExternal Fixedvo

22、ltages1-of-n SelectorSimple DACPro : Digital input. Programmable external voltages.Con : Complex circuit. High speed digital circuits. Many pass gates per data line.Digital Data Driver (三)D0 S0D1 S8D2 S16D3 S24D4 S32D5 S40 S48 S56 S64SCCT1 T2 T3 T4OUTV64 V56 V48 V40 V32 V24 V16 V8 V0Fig3. Sturcture

23、of the SCOLT1 T2T3T476541234Fig4. Waveform of TMSV0V8Fig5. Output Waveform when data is 6nmnVmVVaveragejiAll Digital CircuitGamma Correction of LCDXY取像组件取像电路显像电路显像组件摄像机测受像机测Analog Correction : 2 3 Segment Approach.Digital Correction : External fixed voltage.Gamma Correction Simple CaseXY取像组件取像电路显像电路

24、显像组件摄像机测受像机测TransmissionVoltageThe Block Diagram of the TFT LCD ModuleCCFL BacklightTFT-LCDPANELTiming ControllerScan DriverData DriverRGBCLKHsxVsxTFTLCD ModuleThe TFT LCD Module Type Classified into two kinds by data driver Analog type TFT-LCD module The analog data drivers The analog interface to

25、PC Only NEC Digital type TFT-LCD module The digital data drivers The ADC/ LVDS/PanelLink interface to PC MainstreamThe Analog InterfaceGraphicsControllerTFT-LCDPANELTiming ControllerScan DriverAnalog Data DriverHsVsAnalogRGBAnalogRGBCLKHsxVsxPreAmpLevelShifterControllerPLLPCAnalog ModuleTFTLCD Modul

26、eOSDCCFL BacklightThe ADC InterfaceGraphicsControllerTFT-LCDPANELTiming ControllerScan DriverDigital Data DriverHsVsAnalogRGBDigitalRGBCLKHsxVsxADCBufferControllerPLLPCADC ModuleTFTLCD ModuleOSDCCFL BacklightThe LVDS/PanelLink InterfaceGraphicsControllerLVDS/PanelLinkTxLVDS/PanelLinkRxTFT-LCDPANELTi

27、ming ControllerScan DriverCABLEClockHsVsDigitalRGBDigitalRGBClockHsVsPCTFT-LCD ModuleDigital Data DriverCCFL BacklightAnalog/ADC/LVDS/PanelLink Analog Interface True Color Sampling Error Low Edge Sharpness Noise in the Analog Signal TransmissionAnalog/ADC/LVDS/PanelLink ADC Interface Mainstream in t

28、he Desktop LCD Monitor Interface Sampling Error Low Edge Sharpness Noise in the Analog Signal Transmission EMI Issue for High Resolution Format Low Image Quality and High CostAnalog/ADC/LVDS/PanelLink LVDS Interface Mainstream in the Notebook PC Interface High Edge Sharpness Reducing EMI & Numbe

29、r of Cable Line High Image Quality and Low Cost Short Transmission Length & Low Noise Margin Compatible Issue PanelLink Interface Application in the Desktop LCD Monitor Interface High Edge Sharpness Reducing EMI & Number of Cable Line High Image Quality and Low Cost Second Supply Source IssueAn