第九章同步状态机

1、2022-4-812022-4-822022-4-832022-4-842022-4-852022-4-86StateNext_Statein/outin/out2022-4-872022-4-882022-4-89GF2022-4-810GF2022-4-8112022-4-8122022-4-813Idle Start Stop Clear A/G=0 !A A/F=1 !Reset /F=0 G=0!Reset /F=0 G=0 !Reset | !A/F=0 G=1 状态转移图!Reset /F=0 G=02022-4-8142022-4-8152022-4-8162022-4-817

2、例12022-4-8182022-4-8192022-4-820例22022-4-8212022-4-8222022-4-823module fsm (Clock, Reset, A, F, G);input Clock, Reset, A;output F,G;reg 1:0 state, Nextstate;parameter Idle = 2b00, Start = 2b01, Stop = 2b10, Clear = 2b11;always (posedge Clock) begin if (!Reset) begin state = Idle; end else state = Ne

3、xtstate; end2022-4-824always ( state or A ) begin F=0; G=0; if (state = Idle) begin if (A) Nextstate = Start; else begin Nextstate = Idle; G=1; end end else if (state = Start) if (!A) Nextstate = Stop; else Nextstate = Start;else if (state = Stop) if (A) Nextstate = Clear; else Nextstate = Stop; els

4、e if (state = Clear) begin if (!A) Nextstate = Idle; else Nextstate = Clear; F=1; end else Nextstate= Idle; endendmodule 黄色是我加的，怀疑老师写错了例32022-4-8252022-4-8262022-4-827assign G=state3;assign F=state0;parameter /- G_ i_ j_ F-/ Zero=4b0_0_0_0, Idle=4b0_0_0_0, start=4b0_0_0_0, stop=4b0_0_0_0, clear=4b0_0_0_0,例42022-4-8282022-4-8292022-4-8302022-4-8312022-4-8322022-4-8332022-4-8342022-4-8352022-4-8362022-4-8372022-4-8382022-4-8392022-4-8402022-4-8412022-4-8422022-4-8432022-4-8442022-4-8452022-4-846always (posedge clk) begin if(reset) begin /*置输出为置输出为0*/ end else if