基于EDA的交通灯控制器课程设计报告

1、徽d/打少大学TMYUAN UNIVEHSIIY OF TECHNOLOGY本科课程设计报告课程名称：EDA 计数与FPGAZ用设计设计题目：交通灯控制器实验地点：跨越机房专业班级：电信0901 学号: 2009001249学生姓名：赵宣指导教师：张文爱年 月 日Word资料设计一：三位十进制计数显示器一、设计目的：1、掌握时序电路中多进程的 VHDLI勺描述方法。2、掌握层次化设计方法。3、熟悉EDA勺仿真分析和硬件测试技术。二、设计原理三位十进制计数显示器分三部分完成，先设计十进制计数电路，再设计显示译码电路，最后设计一个顶层文件将两者连接起来。三源程序1、三位十进制计数器的三位分三个进程

2、描述，含有同步清 0信号RESET和计数使能控制信号CINLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COU3 ISPORT(CLK,RESET,CIN:IN STD_LOGIC;CO:OUT STD_LOGIC;A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COU3 ;ARCHITECTURE ART OF COU3 ISSIGNAL AP,BP,CP:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINKK1:PROCE

3、SS(CLK)BEGINIF (CLK'EVENT AND CLK='1') THENIF (RESET='0') THENAP<="0000"ELSIF (CIN='1') THENIF (AP="1001") THENAP<="0000"ELSEAP<=AP+'1'END IF;Word资料END IF;END IF;END PROCESS KK1;KK2:PROCESS(CLK)BEGINIF (CLK'EVENT AND CLK=

4、'1') THENIF (RESET='0') THENBP<="0000"ELSIF (CIN='1') AND (AP="1001") THENIF BP="1001" THENBP<="0000"ELSEBP<=BP+'1'END IF;END IF;END IF;END PROCESS KK2;KK3: PROCESS(CLK)BEGINIF (CLK'EVENT AND CLK='1') THENIF

5、 (RESET='0') THENCP<="0000"ELSIF (CIN='1') AND (AP="1001") AND (BP="1001") THENIF CP="1001" THENCP<="0000"ELSECP<=CP+'1'END IF;END IF;END IF;END PROCESS KK3;PROCESS(CLK) ISBEGINIF CLK'EVENT AND CLK='1' THE

6、NIF AP="1001" AND BP="1001" AND CP="1001" THENCO<='1'ELSECO<='0'END IF;END IF;END PROCESS;A<=AP;B<=BP;C<=CP;END ART;2、七段显示译码电路 VHD段计文件Word资料LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY YIMA7 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);YIMA

7、:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END YIMA7;ARCHITECTURE ART OF YIMA7 ISBEGINPROCESS(A) ISBEGINCASE A ISWHEN "0000"=>YIMA<="1000000”;WHEN "0001"=>YIMA<="1111001”;WHEN "0010"=>YIMA<="0100100”;WHEN "0011"=>YIMA<="01100

8、00”;WHEN "0100"=>YIMA<="0011001”;WHEN "0101"=>YIMA<="0010010”;WHEN "0110"=>YIMA<="0000010”;WHEN "0111"=>YIMA<="1111000”;WHEN "1000"=>YIMA<="0000000”;WHEN "1001"=>YIMA<="00100

9、00”;WHEN OTHERS=>YIMA<="1111111"END CASE;END PROCESS;END ART;3、三位显示译码顶层文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JISHUXIANSHI ISPORT(CLK,RESET,EN:IN STD_LOGIC;SEG1,SEG2,SEG3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END JISHUXIANSHI;ARCHITECTURE ART OF JISHUXIANSHI ISCOMPONENT YIMA7PO

10、RT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT;COMPONENT COU3PORT(CLK,RESET,CIN:IN STD_LOGIC;CO:OUT STD_LOGIC;A,B,C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;SIGNAL IN_A,IN_B,IN_C:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINU0:COU3 PORT MAP(CLK,RESET,EN,IN_A,IN_B

11、,IN_C);Word资料Word资料U1:YIMA7 PORT MAP(IN_A,SEG1);U2:YIMA7 PORT MAP(IN_B,SEG2);U3:YIMA7 PORT MAP(IN_C,SEG3);END ART;四、仿真由图九曲In.勺皿隹2小缶"卜湘3五、下载到电路板得到设计结果显示三位十进制计数设计二：交通灯控制器一、设计要求设计一个由一条支干道和一条主干道的汇合点形成的十字交叉路口的交通灯控制器，主要要求如下：(1).主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。(2)主干道处于常允许状态，两支干道有车来才允许通行。(3)当主、支干道有车时，两者交替通行

12、，主干道每次放行45s,支干道每次放行25s,在每次由亮绿灯变成亮红灯转换过程中，要亮 5s黄灯 作为过渡，并进行减计时显示。二、设计方案1、分模块设计1）、红、绿、黄灯控制模块，模块名 JTDKZ2）、倒计时传输、控制模块 XSKZ3）、倒计时45s CNT45s4）、倒计时25sCNT25s5）、倒计时5sCNT05s6）、输入、输出。2、模块设计思路1）、JTDKZ-根据交通灯显示有4种状态，可以采用CASES句设置选 择4种状态。设置3个输入：CLK时钟脉冲）、SB（支干道传感器）、SM住 干道传感器）。2）、XSK根据需要交通灯显示白不同数倒计时据设置4个输入使能信号：EN45（45

13、s倒计时使能信号）、EN25（25s倒计时使能信号）、EN05（5s 倒计时使能信号）；再设置5个倒计时计数数据输入信号将此时倒计时数据 输出：AIN45M AIN45R AIN25M AIN25R AIN05; 2个输出信号使数码管 显示正在倒计时的时间。3）、CNT45根据倒计时计数的要求设置 3个输入信号：CLK时数脉 冲）、EN45时数使能）、SB（支干道传感器信号）；2个输出DOUT45MDOUT45B 分别用于主、支干道显示。4）、CNT25根据倒计时计数的要求设置 4个输入信号：CLK时数 脉冲）、EN45时数使能）、SM住干道传感器信号）、SB（支干道传感器信号）；2个输 出D

14、OUT25MDOUT25B分别用于主、支干道显示。CLK时数5）、CNT05-根据倒计时计数的要求设置 3个输入信号:脉冲)、EN05B叶数使能)、EN05M计数使能)；1个输出DOUT05用于主、支干道 显示。6)、输入输出模块，3个输入分别为：CLK SB SM 2个输出分别为DOUT17.0、DOUT27.0。三、设计源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ ISPORT(CLK,SM,SB:IN STD_LOGIC;MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);END ENTITY J

15、TDKZ;ARCHITECTURE ART OF JTDKZ ISTYPE STATE_TYPE IS(A,B,C,D);SIGNAL STATE:STATE_TYPE;BEGINCNT:PROCESS(CLK)ISVARIABLE S:INTEGER RANGE 0 TO 45;VARIABLE CLR,EN:BIT;BEGINIF(CLK'EVENT AND CLK='1')THENIF CLR='0'THEN S:=0;ELSIF EN='0'THEN S:=S;ELSE S:=S+1;END IF;CASE STATE ISWHE

16、N A=>MR<='0'MY0<='0'MG0<='1'BR<='1'BY0<='0'BG0<='0'IF(SB AND SM)='1' THENIF S=45 THEN STATE<=B;CLR:='0'EN:='0'ELSE STATE<=A;CLR:='1'EN:='1'END IF;ELSIF(SB AND(NOT SM)='1'THEN ST

17、ATE<=B;CLR:='0'EN:='0'ELSE STATE<=A;CLR:='1'EN:='1'END IF;WHEN B=>MR<='0'MY0<='1'MG0<='0'BR<='1'BY0<='0'BG0<='0'IF S=5 THEN STATE<=C;CLR:='0'EN:='0'ELSE STATE<=B;CLR:='

18、;1'EN:='1'END IF;WHEN C=>MR<='1'MY0<='0'MG0<='0'BR<='0'BY0<='0'BG0<='1'IF(SM AND SB)='1'THENIF S=25 THEN STATE<=D;CLR:='0'EN:='0'ELSE STATE<=C;CLR:='1'EN:='1'END IF;ELSIF SB

19、='0' THEN STATE<=D;CLR:='0'EN:='0'ELSE STATE<=C;CLR:='1'EN:='1'END IF;WHEN D=>MR<='1'MY0<='0'MG0<='0'BR<='0'BY0<='1'BG0<='0'IF S=5 THEN STATE<=A;CLR:='0'EN:='0'ELSE S

20、TATE<=D;CLR:='1'EN:='1'END IF;END CASE;END IF;END PROCESS CNT;END ARCHITECTURE ART;设计仿真的截图：XSKZ莫块的实现A 美电的 配 T简单设计思路：根据EN45 EN25 EN05IM EN05B勺信号以及3个倒计时计数器的计数状态决定输出3个倒计时计数器中某个的状态输出。原理图模块:XSKZDOUW-OJ D0UTB75D)一 EN%-®25一一E1ND5MEHOfiB川N转班7.川«N25Mp.B| J=4N25B|7.0| NN0即刈设计源程序:L

21、IBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CSKZ ISPORT(INA:IN STD_LOGIC;OUTA:OUT STD_LOGIC);END ENTITY CSKZ;ARCHITECTURE ART OF CSKZ ISBEGINPROCESS(INA)ISWord资料BEGINIF INA='1'THEN OUTA<='1'ELSE OUTA<='0'END IF;END PROCESS;END ARCHITEC

22、TURE ART;设计仿真的截图:CNT45锻块的实现简单思路：CLK上升沿到来时，若到计时使能信号和 SB信号有效，CNT45S开始计数，并将输入状态通过 DOUT45MDOUT45盼别输出至U主、支干道显不。设计的原理图模块：CNT45SL .IL- !- SBOailT45Mr.O) 1- r- CLkD0UT46BR .0 - 4- EN45! I ： j.设计源程序：3LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S ISPORT(SB,CLK,EN45:IN

23、STD_LOGIC;DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT45S;ARCHITECTURE ART OF CNT45S ISSIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0);BEGINPROCESS(SB,CLK,EN45) ISBEGINIF SB='0' THEN CNT6B<=CNT6B-CNT6B-1;ELSIF(CLK'EVENT AND CLK='1')THENIF EN45='1'THEN CNT6B<=C

24、NT6B+1;ELSIF EN45='0'THEN CNT6B<=CNT6B-CNT6B-1;END IF;END IF;END PROCESS;PROCESS(CNT6B)ISBEGINCASE CNT6B ISWHEN"000000"=>DOUT45M<="01000101”;DOUT45B<="01010000”;WHEN"000001"=>DOUT45M<="01000100"DOUT45B<="01001001"WHEN&quo

25、t;000010"=>DOUT45M<="01000011”;DOUT45B<="01001000”;WHEN"000011"=>DOUT45M<="01000010"DOUT45B<="01000111"WHEN"000100"=>DOUT45M<="01000001”;DOUT45B<="01000110”;WHEN"000101"=>DOUT45M<="010000

26、00"DOUT45B<="01000101"WHEN"000110"=>DOUT45M<="00111001”;DOUT45B<="01000100”;WHEN"000111"=>DOUT45M<="00111000"DOUT45B<="01000011"WHEN"001000"=>DOUT45M<="00110111”;DOUT45B<="01000010”;WHE

27、N"001001"=>DOUT45M<="00110110"DOUT45B<="01000001"WHEN"001010"=>DOUT45M<="00110101”;DOUT45B<="01000000”;WHEN"001011"=>DOUT45M<="00110100"DOUT45B<="01101001"WHEN"001100"=>DOUT45M<

28、="00110011”;DOUT45B<="00111000”;WHEN"001101"=>DOUT45M<="00110010”;DOUT45B<="0011011T'WHEN"001110"=>DOUT45M<="00110001”;DOUT45B<="00110110”;WHEN"001111"=>DOUT45M<="00110000”;DOUT45B<="0011010T'

29、WHEN"010000"=>DOUT45M<="00101001”;DOUT45B<="00110100”;WHEN"010001"=>DOUT45M<="00101000”;DOUT45B<="0011001T'WHEN"010010"=>DOUT45M<="00100111”;DOUT45B<="00110010”;WHEN"010011"=>DOUT45M<="001

30、00110”;DOUT45B<="0011000T'WHEN"010100"=>DOUT45M<="00100101”;DOUT45B<="00110000”;WHEN"010101"=>DOUT45M<="00100100”;DOUT45B<="0010100T'WHEN"010110"=>DOUT45M<="00100011”;DOUT45B<="00101000”;WHEN"

31、010111"=>DOUT45M<="00100010”;DOUT45B<="0010011T'WHEN"011000"=>DOUT45M<="00100001”;DOUT45B<="00100110”;WHEN"011001"=>DOUT45M<="00100000”;DOUT45B<="0010010T'WHEN"011010"=>DOUT45M<="00011001”;

32、DOUT45B<="00100100”;WHEN"011011"=>DOUT45M<="00011000”;DOUT45B<="0010001T'WHEN"011100"=>DOUT45M<="00010111”;DOUT45B<="00100010”;WHEN"011101"=>DOUT45M<="00010110”;DOUT45B<="0010000T'WHEN"011110&

33、quot;=>DOUT45M<="00010101”;DOUT45B<="00100000”;WHEN"011111"=>DOUT45M<="00010100”;DOUT45B<="0001100T'WHEN"100000"=>DOUT45M<="00010011”;DOUT45B<="00011000”;WHEN"100001"=>DOUT45M<="00010010”;DOUT45B<

34、;="0001011T'WHEN"100010"=>DOUT45M<="00010001”;DOUT45B<="00010110”;WHEN"100011"=>DOUT45M<="00010000”;DOUT45B<="0001010T'WHEN"100100"=>DOUT45M<="00001001”;DOUT45B<="00010100”;WHEN"100101"=>

35、DOUT45M<="00001000”;DOUT45B<="0001001T'WHEN"100110"=>DOUT45M<="00000111”;DOUT45B<="00010010”;WHEN"100111"=>DOUT45M<="00000110”;DOUT45B<="0001000T'WHEN"101000"=>DOUT45M<="00000101”;DOUT45B<="

36、;00010000”;WHEN"101001"=>DOUT45M<="00000100”;DOUT45B<="0000100T'WHEN"101010"=>DOUT45M<="00000011”;DOUT45B<="00001000”;WHEN"101011"=>DOUT45M<="00000010”;DOUT45B<="0000011T'WHEN"101100"=>DOUT45M

37、<="00000001”;DOUT45B<="00000110”;WHEN OTHERS=>DOUT45M<="00000000”;DOUT45B<="00000000”;END CASE;END PROCESS;END;设计仿真的截图:CNT25锻块的实现简单思路：CLK上升沿到来时，若到计时使能信号、 SM言号和SB信号有效，CNT25SF始计数，并将输入状态通过 DOUT25MDOUT25盼别输出至U主、支干道显示设计的原理图模块:设计源程序:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.A

38、LL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT25S ISPORT(SB,SM,CLK,EN25:IN STD_LOGIC;DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S ISSIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINPROCESS(SB,SM,CLK,EN25)ISBEGINIF SB='0'THEN CNT5B<=CNT5B-CNT5B

39、-1;ELSIF SM='0'THEN CNT5B<=CNT5B-CNT5B-1;ELSIF(CLK'EVENT AND CLK='1')THENIF EN25='1'THEN CNT5B<=CNT5B+1;ELSIF EN25='0'THEN CNT5B<=CNT5B-CNT5B-1;END IF;END IF;END PROCESS;PROCESS(CNT5B)ISBEGINCASE CNT5B ISWHEN"00000"=>DOUNT25B<="001001

40、01”;DOUT25M<="00110000”;WHEN"00001"=>DOUNT25B<="00100100”;DOUT25M<="00101001”;WHEN"00010"=>DOUNT25B<="00100011”;DOUT25M<="00101000”;WHEN"00011"=>DOUNT25B<="00100010”;DOUT25M<="00100111”;WHEN"00100&quo

41、t;=>DOUNT25B<="00100001”;DOUT25M<="00100110”;WHEN"00101"=>DOUNT25B<="00100000”;DOUT25M<="00100101”;WHEN"00110"=>DOUNT25B<="00011001”;DOUT25M<="00100100”;WHEN"00111"=>DOUNT25B<="00011000”;DOUT25M<=&qu

42、ot;00100011”;WHEN"01000"=>DOUNT25B<="00010111”;DOUT25M<="00100010”;WHEN"01001"=>DOUNT25B<="00010110”;DOUT25M<="00100001”;WHEN"01010"=>DOUNT25B<="00010101”;DOUT25M<="00100000”;WHEN"01011"=>DOUNT25B<

43、="00010100”;DOUT25M<="00011001”;WHEN"01100"=>DOUNT25B<="00010011”;DOUT25M<="00011000”;WHEN"01101"=>DOUNT25B<="00010010”;DOUT25M<="00010111”;WHEN"01110"=>DOUNT25B<="00010001”;DOUT25M<="00010110”;WHEN&q

44、uot;01111"=>DOUNT25B<="00010000”;DOUT25M<="00010101”;WHEN"10000"=>DOUNT25B<="00001001”;DOUT25M<="00010100”;WHEN"10001"=>DOUNT25B<="00001000”;DOUT25M<="00010011”;WHEN"10010"=>DOUNT25B<="00000111”;DO

45、UT25M<="00010010”;WHEN"10011"=>DOUNT25B<="00000110”;DOUT25M<="00010001”;WHEN"10100"=>DOUNT25B<="00000101”;DOUT25M<="00010000”;WHEN"10101"=>DOUNT25B<="00000100”;DOUT25M<="00001001”;WHEN"10110"=>

46、;DOUNT25B<="00000011”;DOUT25M<="00001000”;WHEN"10111"=>DOUNT25B<="00000010”;DOUT25M<="00000111”;WHEN"11000"=>DOUNT25B<="00000001”;DOUT25M<="00000110”;WHEN OTHERS=>DOUNT25B<="00000000”;DOUT25M<="00000000”;END

47、 CASE;END PROCESS;END;设计仿真的截图：9.825 ns ±l Pointer:168.3 ns Interval:End:158.48 ns Start:N：dITlH_oCLEC_1EN25_2SB_3SM D0UT25L 13国 D0UT25Master Time Bar:J pE9.825 ns,J80.0 ns160.0 ns240. 0 ns320.0 ns400.0 ns480.0 ninusin比TZ1It：1 i1611514 儿 131211111yxLiyIJBT：'：ZF.4J1 :阳19,116 11716IJ6CNT05S莫块的

48、实现简单思路：CLK±升沿到来时，若到计时使能信号有效，CNT25班始计数，并将输入状态通过 DOUT0输出到主、支干道显示。设计的原理图模块：rmjr riiBjr-m vimiBiiHiBinniiBiBiim nniBiBiraiBimiBin ：CNTD5Sl CLK DOiUTSp.D !- EN05M EN056 t-E 循ST设计源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LO

49、GIC;DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT05S;ARCHITECTURE ART OF CNT05S ISSIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(CLK,EN05M,EN05B)ISBEGINIF(CLK'EVENT AND CLK='1')THENIF EN05M='1'THEN CNT3B<=CNT3B+1;ELSIF EN05B='1'THEN CNT3B<=CNT3B+1;ELSIF EN0

50、5B='0'THEN CNT3B<=CNT3B-CNT3B-1;END IF;END IF;END PROCESS;PROCESS(CNT3B)BEGINCASE CNT3B ISWHEN"000"=>DOUT5<="00000101”;WHEN"001"=>DOUT5<="00000100”;WHEN"010"=>DOUT5<="00000011”;WHEN"011"=>DOUT5<="00000010”

51、;WHEN"100"=>DOUT5<="00000001”;WHEN OTHERS=>DOUT5<="00000000”;END CASE;END PROCESS;END;设计仿真的截图：Word资料显示译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY YIMA7 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);YIMA:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END YIMA7;ARCHITECTURE ART OF

52、YIMA7 ISBEGINPROCESS(A) ISBEGINCASE A ISWHEN "0000"=>YIMA<="1000000”;WHEN "0001"=>YIMA<="1111001”;WHEN "0010"=>YIMA<="0100100”;WHEN "0011"=>YIMA<="0110000”;WHEN "0100"=>YIMA<="0011001”;WHEN "

53、;0101"=>YIMA<="0010010”;WHEN "0110"=>YIMA<="0000010”;WHEN "0111"=>YIMA<="1111000”;WHEN "1000"=>YIMA<="0000000”;WHEN "1001"=>YIMA<="0010000”;WHEN "1010"=>YIMA<="0001000”;WHEN "

54、;1011"=>YIMA<="0000011”;WHEN "1100"=>YIMA<="1000110”;WHEN "1101"=>YIMA<="0100001”;WHEN "1110"=>YIMA<="0000110”;WHEN "1111"=>YIMA<="0001110”;WHEN OTHERS=>NULL;END CASE;Word资料END PROCESS;END ART;整体组装

55、和测试自动转换出来的源程序：LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY work;ENTITY Block1 ISport(CLK : IN STD_LOGIC;SM : IN STD_LOGIC;SB : IN STD_LOGIC;MR : OUT STD_LOGIC;MY : OUT STD_LOGIC;MG : OUT STD_LOGIC;BR : OUT STD_LOGIC;BY : OUT STD_LOGIC;BG : OUT STD_LOGIC;DOUT1 : OUT STD_LOGIC_VECTOR(7 downto 0);D

56、OUT2 : OUT STD_LOGIC_VECTOR(7 downto 0);END Block1;ARCHITECTURE bdf_type OF Block1 IScomponent cnt05sPORT(CLK : IN STD_LOGIC;EN05M : IN STD_LOGIC;EN05B : IN STD_LOGIC;DOUT5 : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component cnt25sPORT(SB : IN STD_LOGIC;SM : IN STD_LOGIC;CLK : IN STD_LOGIC;EN

57、25 : IN STD_LOGIC;DOUT25B : OUT STD_LOGIC_VECTOR(7 downto 0);DOUT25M : OUT STD_LOGIC_VECTOR(7 downto 0);end component;component cnt45sPORT(SB : IN STD_LOGIC;CLK : IN STD_LOGIC;EN45 : IN STD_LOGIC;DOUT45B : OUT STD_LOGIC_VECTOR(7 downto 0);DOUT45M : OUT STD_LOGIC_VECTOR(7 downto 0);end component;comp

58、onent jtdkzPORT(CLK : IN STD_LOGIC;SM : IN STD_LOGIC;SB : IN STD_LOGIC;MR : OUT STD_LOGIC;MY0 : OUT STD_LOGIC;MG0 : OUT STD_LOGIC;BR : OUT STD_LOGIC;BY0 : OUT STD_LOGIC;BG0 : OUT STD_LOGIC);end component;component xskzPORT(EN45 : IN STD_LOGIC;EN25 : IN STD_LOGIC;EN05M : IN STD_LOGIC;EN05B : IN STD_L

59、OGIC;AIN05 : IN STD_LOGIC_VECTOR(7 downto 0);AIN25B : IN STD_LOGIC_VECTOR(7 downto 0);AIN25M : IN STD_LOGIC_VECTOR(7 downto 0);AIN45B : IN STD_LOGIC_VECTOR(7 downto 0);AIN45M : IN STD_LOGIC_VECTOR(7 downto 0);DOUTB : OUT STD_LOGIC_VECTOR(7 downto 0);DOUTM : OUT STD_LOGIC_VECTOR(7 downto 0);end compo

60、nent;signal SYNTHESIZED_WIRE_13 : STD_LOGIC;signal SYNTHESIZED_WIRE_14 : STD_LOGIC;signal SYNTHESIZED_WIRE_15 : STD_LOGIC;signal SYNTHESIZED_WIRE_16 : STD_LOGIC;signal SYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(7 downto 0);signal SYNTHESIZED_WIRE_9 : STD_LOGIC_VECTOR(7 downto 0);signal SYNTHESIZED_WIRE_10 : STD_LOGIC_VECTOR(7 downto 0);signal SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(7 downto 0);signal SYNTHESIZED_WIRE_12 : STD_LOGIC_VECTOR(7 downto 0); BEGINMY <= SYNTHESIZED_WIRE_13;MG <= SYNTHESIZED_WIRE_16;BY <= SYNTHESI