用VHDL语言编写的频率计程序

1、用VHDL语言编写的频率计程序分频entity FP isport( clk,rst:in std_logic;fp:out std_logic);end FP;Architecture behave of FP issignal cnt: std_logic_Vector(15 downto 0);signal tmp,temp: std_logic;beginprocess(clk,rst)BEGINif Rst='1' thencnt<="0000000000000000"elsif clk'event and clk='1

2、9; thenif cnt="0000001111111111" then cnt<="0000000000000000" elsecnt<=cnt + 1;end if;end if;end process;process(clk,rst)beginif clk'event and clk='1' thenif cnt="0000001111111111" then tmp<=not tmp;end if;end if;end process;process(clk,rst)beginif

3、clk'event and clk='1' thenif cnt="0000000111111111" then temp<= not temp;end if;end if;end process;fp<= tmp XOR temp;end behave;计数Entity FRE is port( clk,CLR,EN:in std_logic;COUT:out std_logic;CQ:out std_logic_Vector(3 downto 0); end FRE;Architecture behave of FRE issigna

4、l QN: std_logic_Vector(3 downto 0); beginprocess(clk,CLR)BEGINIF CLR='0' thenQN<="0000"ELSIF clk'event and clk='1' then if en='1' thenif QN="1001" thenQN<="0000"COUT<='1'elseQN<=QN+1;COUT<='0'end if;end if;END I

5、F;end process; CQ(3 DOWNTO 0)<=QN;end behave;控制library IEEE;entity CTL isport( clk:in std_logic;EN,CLR,FINISH:out std_logic); end CTL;Architecture behave of CTL issignal DIV: std_logic;beginprocess(clk)BEGINif clk'event and clk='1' then DIV<= NOT DIV;end if;end process;EN<=DIV;F

6、INISH<=NOT DIV; PROCESS(DIV,CLK)BEGINIF DIV='0' AND CLK='0' THEN CLR<='0'ELSECLR<='1'END IF;end process;end behave;显示Entity DISPLAY is port( clk:in std_logic;DATA:in std_logic_Vector(15 downto 0); SD:out std_logic_Vector(7 downto 0); SS:out std_logic_Vector(1

7、 downto 0);end DISPLAY;Architecture behave of DISPLAY issignal C: std_logic_Vector(1 downto 0);signal KEYBUF: std_logic_Vector(3 downto 0);beginprocess(clk)BEGINif clk'event and clk='1' thenC<=C+1;end if;end process;SS<=C;PROCESS(C)BEGINCASE C ISWHEN "00" => KEYBUF<

8、=DATA(15 downto 12); WHEN "01" => KEYBUF<=DATA(11 downto 8); WHEN "10" => KEYBUF<=DATA(7 downto 4); WHEN "11" => KEYBUF<=DATA(3 downto 0); WHEN OTHERS => KEYBUF<="0000"END CASE;END PROCESS;PROCESS(KEYBUF)BEGINcase KEYBUF iswhen "00

9、00" => SD<="00111111"when "0001" => SD <="00110000"when "0010" => SD <="01011011"when "0011" => SD <="01001111"when "0100" => SD <="01100110"when "0101" => SD <

10、;="01101101"when "0110" => SD <="01111100"when "0111" => SD <="00000111"when "1000" => SD <="01111111"when "1001" => SD <="01101111"when "1010" => SD <="01110111&quo

11、t;when "1011" => SD <="01111100"when "1100" => SD <="00111001"when "1101" => SD <="01011110"when "1110" => SD <="01111011"when "1111" => SD <="01110001"when others => SD <="00000000"END CASE;END PROCESS;end behave;显示控制entity REG isport( LOAD:in std_logic;QIN:in std_logic_Vector(15 downto 0); QOUT:o