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1、international center on design for nanotechnologies(ic-dfn)http:/ summaryestablish an international center on design for nanotechnologies (ic-dfn)project focus design methodologies systems-level issues international collaboration to leverage global investment and coordinate researchhttp:/ research t

2、eamusucla: jason cong (center co-director) and kang wanguc santa barbara: tim cheng (center co-director) and evelyn hutaiwannational tsinghua university (nthu): shih-chieh chang (taiwan coordinator) cheng chung chi, shi-yu huang, tingting hwang, youn-long lin, c. l. liu, cheng-wen wunational taiwan

3、university (ntu): yao-wen chang, juin-lang huang, chien-mo li, ric huangchinatsinghua university (thu): jinian bian, xianlong hong (china coordinator)peking university (pku): xu cheng, ru huangzhejiang university (zju): xiaolang yan, zhizhen yehttp:/ of research and educational taskshttp:/ overview

4、thrust 1: technology and architecture/platform driver technology driver architecture/platform driver:nano-fpgathrust 2: design for nano-technology design for robustness enable higher level of abstraction efficient solutions to fundamental design automation problemsthrust 3: design/application driver

5、 multi-core heterogeneous soc design in nanotechnologieshttp:/ 1(a): technology driver (led by kang wang and evelyn hu) technology characterization, in terms of reliability, process variation, etc. (ucsb, zju) design of circuit blocks, e.g. memory cells, logic gates, and multiplexors (ucla, pku) bot

6、tom-up assembly techniques (ucsb, nthu)http:/ 1(b) architecture/platform driver:nano-fpga (led by jason cong and kang wang) technology characterization, in terms of reliability, process variation, etc. (ucla, ucsb, zju) exploration of reconfiguration technologies (pku and ucla) circuit-level design

7、of nano-fpga (pku and ucla) logic-level design of nano-fpga (ucla and nthu) basic design flow for mapping gate-level circuits to nano-fpgas (ucla, ntu and thu)http:/ 2(a) design for robustness (led by tim cheng) exploring tradeoffs between reconfiguration and redundancy for reliable design (ucsb) on

8、-line/off-line self-test and self-diagnosis to support reconfiguration (ucsb) architectural design for timing-error-tolerance (nthu, ntu, and ucsb) functional error tolerance for nano-fpga and nano-structured asic (nthu) cad issues on synthesis, mapping, and routing of reliable design with built-in

9、reconfiguration and redundancy capabilities (nthu, ntu, and zju) http:/ 2(b) enable higher level of abstraction(led by jason cong) system-level performance modeling and estimation (ucla) system-level and behavior-level synthesis (ucla and thu) system-level and behavior-level property check and equiv

10、alence checking (ucsb)http:/ 2(c): efficient solutions to fundamental design automation problems efficient high-level satisfiability checking (ucsb) multilevel optimization (ucla and ntu) efficient solver for large-scale linear systems (thu and nthu) multi-space search and search space smoothing (th

11、u)http:/ 3 design driver(led by prof. youn-long lin)multi-core heterogeneous soc design in nanotechnologies cpu core designs (pku), dsp core designs (zju), and video codec designs (nthu) on-chip interconnect structure design (nthu)http:/ by prof. cheng, prof. hu and prof. cong) semi-annual workshops

12、 (locations rotating among the u.s., mainland china and taiwan) web seminars establishment of international internships partnership with uc eap program, joint activities with ipam (ucla) and cms (zju) providing seminars to wise and/or mesa and participate in cnsis inset and epsem programshttp:/ of y

13、ears 1 & 2 (us team) thrust 1: technology and architecture/platform driver technology driver architecture/platform driver:nano-fpgathrust 2: design for nano-technology design for robustness enable higher level of abstraction efficient solutions to fundamental design automation problemsthrust 3: design/application driver multi-core heterogeneous soc design in nanotechnologieshttp:/ collaboration activitiesproposal planning meetings on n

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