总线技术与虚拟仪器课件

Chapter2VirtualInstruments虛擬儀器概念

虛擬儀器的組成虛擬儀器的體系結構虛擬儀器的特點典型的虛擬儀器系統2.1ConceptofVITraditionalInstrumentVirtualInstrument信號的採集與控制信號的分析與處理結果的表達與輸出Definition虛擬儀器主要是以電腦為核心，通過最大限度地利用電腦系統的軟體和硬體資源，使電腦在儀器中不但能象在傳統程式控制化儀器中那樣完成過程控制、數據運算和處理工作，而且可以用強有力的軟體去代替傳統儀器的某些硬體功能，直接產生出激勵信號或實現所需要的各項測試功能。

Softwareistheinstrument

2.2ArchitectureofVIInput Signalconditioningandconversionofanincominganalogwaveformtodigitalformatforprocessing.OutputConversionofdigitaldatatoananalogwaveformalongwithnecessarysignalconditioning.DataProcessingAmicroprocessororDSP(DigitalSignalProcessing)ExampleofVIsA/DDSP9.99VoltmeterSpectrumAnalyzerDigitalOscilloscopeDSPD/AARBFunctionGeneratorPulseGenerator虛擬儀器組成上的特點軟體和硬體功能的模組化軟體和硬體功能的分層

儀器功能的軟體化

虛擬儀器的功能可以借助電腦軟體來生成

SUMMARY虛擬儀器的層次化結構VIVIVIVIVIVIVIInstrumentDriverInstrumentHardwareInstrumentDriverInstrumentHardwareSummary虛擬儀器是這樣的一種儀器系統：在用戶需要某種測試功能時，可由用戶自己通過電腦平臺利用圖形軟體對測量模組進行分層組合，以生成所需要的測試功能。

2.3ConstructionofVIInstrumentHardwareProcessorMemoryDisplayApplicationSoftwareInstrumentDriverDevelopmentEnvironmentUserInterfaceUserComputerHardwareTypicalVISystemsInstrumentDriverAninstrumentdriverisasoftwaremodulethathandlesthedetailsofcontrollingandcommunicatingwithaspecificinstrument.AsetofsoftwareroutinesControllingaprogrammableinstrument

WritteninLabVIEWorLabWindows/CVI

ProvidedbyapplicationsoftwaresuppliersDevelopmentEnvironmentGraphicalProgrammingLabWindows/CVIVisualBasicLaboratoryVirtualInstrumentEngineeringBenchComponentWorksHPVEEStandardANSIC

Language2.4PerformanceadvantagesBetteraccuracyandrepeatabilityMeasurementspeedSimplifiedswitchingandcablingShortenedsystemintegrationtimeUser-definedmeasurementfunctionsFutureexpansionComparisonwithTraditionalInstrument融合了電腦強大的硬體功能利用了電腦豐富的軟體資源利用電腦匯流排、儀器匯流排和工業標準匯流排利用電腦網絡技術開放式標準體系ExampleofaVI(Ⅰ)ExampleofaVI(Ⅱ)FrontPanelBlockDiagram2.5TypicalVIsystemsPC-basedVIsystemDataacquisitionsystemRS232USBIEEE1394GPIBVXIbussystemPXIsystemDAQsystemDAQ儀器的優越性利用PC技術設計手段靈活性價比高性能選擇範圍大大量的軟體工具可用DAQ儀器什麼是DAQ儀器？DAQ儀器的組成方式插入式外掛式直接外掛式DAQ儀器與匯流排DAQ儀器DAQ儀器設計的關鍵技術匯流排擴展與介面技術A/D、D/A轉換技術多路開關和濾波放大技術高速緩存技術即時採樣技術可編程邏輯器件與邏輯控制電路DAQ儀器的發展RS232Serial,cablebusfreeonPCsOldestandmostcommoninterfaceDifficulttoconfigureBaudrate,parity,numberofstopbits,etc.Notmultidrop–oneinstrumentperportShorttransmittingdistanceUSBPervasivePCstandardFour-wire,serial,cablebusintendedtoreplacePCserialportsSupportsisochronousandasynchronoustransfersEasytousePlugandPlay -HotpluggableCable-powered -Errordetectionandretries

IEEE1394High-speed,high-latencyserialcablebusMany"standards"Fourwirevs.SixwirePopularforAVequipmentCompeteswithUSB2.0GPIB匯流排GENERALPURPOSEINTERFACEBUS第三章GPIB3.1匯流排技術3.2GPIB概述3.1匯流排技術定義匯流排是一組信號線的集合，是指從任意一個源點到任意一個終點的一組傳送數字信號的公共通道。

例：微型電腦系統匯流排標準OfficialstandardsDefactostandards3.1.1匯流排標準的基本內容機械結構規範規定模組尺寸、匯流排插頭、連接器等的規格

功能結構規範數據線、地址線、讀／寫控制邏輯線、時鐘線以及電源線、地線等

中斷機制

匯流排主控仲裁

應用邏輯，如握手聯絡線、複位、自啟動、休眠維護等

3.1.1匯流排標準的基本內容電氣規範規定信號邏輯電平、負載能力及最大額定值、動態轉換時間等

3.1.2匯流排分類按使用範圍分電腦匯流排測控匯流排儀器匯流排現場匯流排網路通信匯流排按數據傳送方式分位並行匯流排8位、16位及32位等

位串行匯流排3.1.2匯流排分類按其規模、用途及應用場合

片內匯流排片匯流排IBMPC、ISA和

PCI

系統匯流排STD和VME

通信匯流排RS232和USB，IEEE-488和VXI，Centronics

3.1.3採用標準匯流排的優點簡化系統設計；簡化系統結構，提高系統可靠性；

便於系統的擴充和更新；能得到多家廠商的支持，便於組織生產，便於維修，經濟性好。3.1.4

匯流排的數據傳輸

一次數據傳輸經歷的4個階段

申請仲裁（arbitration）佔用匯流排階段尋址（addressing）階段數傳（datatransfering）階段結束（ending）階段3.1.4

匯流排數據傳輸匯流排傳輸的控制方式

同步傳輸

非同步傳輸

半同步傳輸

3.1.5

匯流排的發展趨勢

傳輸速率不斷提高

降低功耗

功能結構不斷調整更新

3.2

GPIB概述

Introduction

ExampleofGPIBsystem

TypesofGPIBmessages

Talkers,listeners&controllers

GPIBsignals&lines

Physical&electricalcharacteristics

IEEE488.2&SCPI3.2.1Introduction3.2.1IntroductionHP設計HP-IB196519751987199019921993HP-IB成為IEEE488IEEE488.1-1987IEEE488.2SCPI被引入IEEE488修訂IEEE488.2NI提出HS488StandardCommandsforProgrammableInstruments3.2.1Introduction從1975年就成為編程的標準8位的並行協議傳輸率低於1Mbytes/s標準電纜最多控制14臺儀器有大量支持其標準的儀器3.2.2ExampleofGPIBSystem3.2.3TypesofGPIBMessages

Device-dependentmessages

OftencalleddataordatamessagesInterfacemessages

Usuallycalledcommandsorcommandmessages3.2.4Talkers,Listeners&Controllers

Talker

sendsdatamessagestooneormoreListeners.Listener

receivesthedata.Controller

managestheflowofinformationontheGPIBbysendingcommandstoalldevices.3.2.5GPIBsignals&lines3.2.5GPIBsignals&linesDataLinesD0throughD7dataandcommandmessagesAttention(ATN)line7-bitASCIIorISOcodeset3.2.5GPIBsignals&lines

HandshakeLines

asynchronouslycontrolthetransfer3-wireinterlockedhandshakeNRFD(notreadyfordata)ListenersDAV(datavalid)ControllerortalkerNDAC(notdataaccepted)Listeners3.2.5GPIBsignals&lines

InterfaceManagementLinesATN(attention)ATN=0 dataATN=1 commandsoraddressIFC(interfaceclear)REN(remoteenable)SRQ(servicerequest)EOI(endoridentify)EOI=1,ATN=0 theendofamessagestring EOI=1,ATN=1 identifydevices 3.2.6Physical&ElectricalCharacteristics24-conductorcable

bothaplugandreceptableconnectorateachend

negativelogicwithstandardTTLlevelsIEC6253.2.6Physical&ElectricalCharacteristicsLinearConfigurationStarConfiguration3.2.6Physical&ElectricalCharacteristicsFornormaloperation:Amaximumseparationof4mbetweenanytwodevicesandanaverageseparationof

2movertheentirebusAmaximumtotalcablelengthof

20m

Nomorethan15deviceloadsconnectedtoeachbus,withnolessthantwo-thirdspoweredon3.2.7IEEE488.2&SCPIIEEE488.1

Forthefirsttime,instrumentsfromdifferentmanufacturerswereinterconnectedbyastandardcable.IEEE488.2

TheIEEE488.2standardfocusesmainlyonthesoftwareprotocolissues.SCPI

SCPIbuiltontheIEEE488.2standardanddefineddevice-specificcommandsthatstandardizeprogramminginstruments.VXIVMEbuseXtensionsforInstrumentation1TheNeedforVXIbusPhysicalsizereductionofrack-and-stackinstrumentationsystems

Tightertimingandsynchronizationbetweenmultipleinstruments

Fastertransferrates

VXIusesstandardtechnologyGPIBVMEbusWhatisVXI?TheVXIConsortiumwasformedin1987definingamulti-vendorinstrument-on-a-cardstandard

TheIEEEofficiallyadoptedtheVXIspecification,IEEE1155,in1993

TheVXIplug&playSystemsAlliance,foundedinSeptember1993

SeekingahigherlevelofsystemstandardizationtocoverallVXIsystemcomponents

VXIisbackedbymorethan250vendors,withmorethan10000productsavailable

VXIbringsthefollowingbenefitsOpen,multi-vendorstandardsmaximizeflexibility

Modular,ruggeddesignimprovesreliabilitySmallersizeandhigherdensityreducefloorspace,enhancemobilityorportability

Moreprecisetimingandsynchronizationimprovemeasurementcapability

StandardizedVXIplug&playsoftwareeasessystemconfiguration,programmingandintegration

VXIbusMechanicalConfigurationVXIbusmechanicalspecificationPackagingrequirementsElectromagneticcompatibilityPowerdistribution,coolingandairflow

forVXIbusmainframesandplug-inmodulesVXIModuleSizes

P2（任選）P3（任選）P1A(100×160×20)B(233.35×160×20)(233.35×340×30)D(366.7×340×30)CVXIbus的匯流排構成

VME電腦匯流排時鐘和同步匯流排星形匯流排觸發匯流排本地匯流排模擬和匯流排模組識別匯流排電源線

VME系統的匯流排VMEbusSignalLinesDataTransferBus（DTB）DTBArbitrationBusPriorityInterruptBusUtilityBus數據傳輸匯流排尋址線地址線A01~A31地址修改線AM0*~AM5*數據選通線DS0*~DSl*字長線LWORD*數據線D00~D31控制線地址選通AS*數據選通線DS0*~DS1*匯流排錯誤線BERR*數據傳輸應答線DTACK*讀/寫信號線WRITE*尋址方式短地址尋址64K位元組標準地址尋址64M位元組擴展地址尋址4G位元組DTB仲裁匯流排匯流排請求線BRX*匯流排允許輸入線BGXIN*匯流排允許輸出線BGXOUT*

以上3種信號線中X取值0、1、2、3四種匯流排忙線BBSY*匯流排清除線BCLR*

匯流排請求仲裁鏈

BGXIN*

1號槽BGXOUT*BGXIN*

2號槽BGXOUT*BGXIN*

3號槽BGXOUT*BGXIN*

4號槽BGXOUT*仲裁模組無匯流排請求匯流排請求無匯流排請求BG2IN*

1號槽BG2OUT*BG2IN*

2號槽BG2OUT*BG2IN*

3號槽BG2OUT*BG2IN*

4號槽BG2OUT*仲裁模組低低高高匯流排請求高匯流排請求仲裁仲裁鏈中每個模組的匯流排允許輸出信號與匯流排請求及匯流排允許輸入信號有如下邏輯關係：優先中斷匯流排

中斷請求線IRQl*~IRQ7*中斷應答線IACK*中斷應答輸入線IACKIN*中斷應答輸出線IACKOUT*

優先中斷匯流排系統控制板CPU板IACK菊花鏈驅動中斷管理中斷中斷IACK*背板IACKIN*IACKIN*IACKIN*IACKIN*IACKOUT*IACKOUT*IACKOUT*IACKOUT*優先中斷匯流排每個中斷模組的中斷應答輸出信號與其中斷應答輸入及中斷請求信號間有如下邏輯關係：公用匯流排系統時鐘線SYSCLK序列時鐘線SERCLK序列數據線SERDAT*交流故障線ACFAIL*系統複位線SYSRESET*系統故障線SYSFAIL*

VXIVMEbuseXtensionsforInstrumentation2ECL電平發射極耦合數字積體電路（EmitterCoupledLogicIC）電晶體工作在非飽和狀態的電流開關電路由於電路工作時電晶體工作點不進入飽和區，存貯時間為零，因而它是目前速度最高的邏輯積體電路，平均傳輸延遲時間可以達到1ns左右，為超高速電路。邏輯靈活性大工作頻率高（一般可達幾百兆赫，最高可達1.5GHz）廣泛用於高速大型電腦、數字通信系統，高精度測試設備等方面.

主要缺點是功耗大、雜訊容限低、成本高。

預備知識ECL電平ECL的正電源電壓為VCC，負電源電壓VEE。為了提高電路的抗干擾能力，應將VCC接地，即採用負電源供電。對於標準的ECL電路，規定VCC=0V，VEE=-5.2V，輸出高電平VOH=-0.9V，輸出低電平VOL=-1.75V。VXIbus的匯流排構成

VME電腦匯流排時鐘和同步匯流排星形匯流排觸發匯流排本地匯流排模擬和匯流排模組識別匯流排電源線

CLOCKANDSYNCMODIDLINESSTARLINESVMEBUSTRIGGERBUSSUMBUSLOCALBUSVXIbusesVMEbusSignalLinesDataTransferBus（DTB）DTBArbitrationBusPriorityInterruptBusUtilityBus825ΩMODID00MODID01~12LBUSCLBUSALBUSCCLK100槽+-CLK101槽CLK102槽50Ω50ΩMODID01MODID02-++-LBUSALBUSCP2引腳上的CLK10，MODID及LBUS線連接10MHzSystemClockTheSlot-0Controllerisresponsibleforgeneratingthe10MHzsystemclockP2connectorDifferentialECLsignal10-MHzsquarewavewithaminimumaccuracyof±0.01%CLK100:P3connectorSYNC100:P3connectorLocalBusP2connecter:12-linebus,250Mbytes/sP3connecter:24-linebus,1Gbytes/sConnectingLBUS-row-CpinsofslotNtoLBUS-row-ApinsofslotN+1ProvidingaconvenientwayofprovidingaprivatecommunicationspathbetweenmodulesSixclassesaredefinedTTL,ECL,Analoglow,medium,andhigh.Oneclassisreserved模組識別線MODID用來檢測模組的存在並指示它的物理位置從0號槽出發被引至1~12槽P2連接器發出MODID01~12共12條信號線，對1~12槽的模組進行識別0號槽通過被檢測模組上一個825Ω接地電阻將MODID線下拉到低電平來檢測該模組的存在TriggerLines2ECLand8TTLtriggerlinesthatareavailableateachslotinthebackplaneDrivenbyanymoduleinthemainframeUsefulfordistributingclockandtiminginformationonachassis-widebasis6triggerlineprotocolsaredefinedTriggerLinesTTLtriggerlinesvsECLtriggerlines8TTLtriggerlinesTTLTRG0*-TTLTRG7*P2connector12.5MHzor12.5Mbytes/s6ECLtriggerlinesECLTRG0–ECLTRG5P2&P350/62.5MHzor50/62.5Mbytes/sStarlinesStarLinesP3connectorDifferentialECLsignalsSTARX+,STARX-,STARY+,STARY-12PAIRSSTARXSTARYLINESSlot0=Switchmatrix

AnalogSUMBUSA50

ΩterminatedbusDrivenbycurrentsourcesAsignalsourceshouldhavethecapabilitytodriveandreceivefromthenodeVXIAdvantagesModularformatFastdatatransferInstrumentationBussesDisadvantagesHighCostSizeAgilent34401ADMManditsVXIbusC-Sizeequivalent,theAgilentE1412AAComparisonofToday'sInstrumentationPlatformsGPIBVXIStandardPCsPXITransferWidth

(bits)88,16,328,16(ISA);8,16,32,64(PCI)8,16,32,64Throughput

(Mbytes/s)140

80(VME64)1-2(ISA)

132-264(PCI)132-264Timingandsyn-chronizationNoneDefinedProprietaryDefinedProductAvailability>10,000>1000>10,000~1000SizeLargeMediumSmall-MediumSmall-MediumStandardsoft-wareframeworksNoneVXIplug&playDefinedNoneDefinedModularNoYesNoYesEMIShieldingOptionalDefinedBoardSpecificModuleSpecificSystemCostHighMedium-HighLowLow-MediumVXI匯流排系統的資源管理資源管理者0槽器件ResourceManagerFunction•IdentifyallVXIbusdevicesinthemainframe.•Managethesystemselftestanddiagnosticsequence.•Configurethesystem’saddressmaps.•AllocatetheVMEbusIRQlines.•InitiatenormalsystemoperationSlot-0Controller•Provideclockgeneration(10MHzclockC-andD-size,and100MHzD-size).•ProvideMODIDLines.ProvideStarLines.VXI匯流排的典型系統結構HardwareOverviewEmbeddedcontrollersRemotecontrollersVXIpcMXI,GPIB,USB,orIEEE1394VXIpc-870EmbeddedControllerDesktopPCina2slotVXIchassisPentiumIII,450MHzPCIexpansionslotorinternalCD-ROMCompleteperipheralsetGPIB,parallelport,2serialports,2USBports,10/100BaseTEthernet,UltraWideSCSI-3,keyboard&mouseports,PCcard,floppyRemoteVXIControllersPCI-MXI-2–highestoverallperformanceofanyremotecontrolsolutionforVXIVXI-1394–convenient,economicalcontrolofVXI(andGPIB)GPIB-VXI–addVXIframestoGPIBsystems,affordablyPC’sForVXIControlPC’susethelatesttechnologyHighperformancemicroprocessorsPentiumPCIlocalbusarchitectureHighperformanceperipheralsPlentifulandeasytousesoftwareAttractivecost/performanceratioWhyPCI?Highperformance132Mbytes/sfor32bittransfers64-bitinterfacealreadydefinedIndustrystandardperipheralexpansionApple,DEC,IBM,Motorola,Sun,HPPCsDell,Compaq,andsoonPeripheralComponentInterconnectPCI-MXI-2PCI-MXI-2VXI-MXI-2(32-bit)(64/32-bit)(32-bit)PCIMXI-2VXIVXIPCIIEEE1394HostAdapterVXI-1394(32-bit)(32-bit)IEEE1394serialVXI-1394GPIB-VXIPCI-GPIBGPIB-VXI/C(32-bit)(8-bit)(32-bit)“*IDN?”PCIGPIBVXIVXI匯流排器件寄存器基器件記憶體基器件消息基器件擴展器件

VXIbus層通信協議配置寄存器通信寄存器共用記憶體協議字串行協議VXI488.2語法器件特定協議器件特定協議器件特定協議器件特定協議Multi-systemeXtensionsforInstrumentsMXIVirtualInstrumentationviaPCControlHS488-8MB/sGPIB>1MB/sMXI-3~100MB/sMXI,MXI-2>10MB/sMXITodayOpenspecificationVXIplug&playcoretechnologyMXIhasbeensuccessfulfortheindustryMainframe-to-mainframeexpansionDefactostandardtoextendVXImainframesDesktopcomputercontrolofVXImainframesMainframeMXI-2VXI-MXI-2IntelPCI-MXI-2VXI-MXI-2(32-bit)(64/32-bit)(32-bit)PCIMXI-2VXIMXI-2ProductsNewproductsbasedontheMXIversion2.0PCI-MXI-2Highperformance33Mbytes/sburst23Mbytes/ssustainedVXI-MXI-2,VME-MXI-2VME64PCI-MXI-2VXI-MXI-2MXI-2KeyFeaturesHighperformanceSynchronousMXI,VME64DMADirectcontrolofVXIbusInterrupts,Triggers,CLK10,andsoonOptionalDRAMSoftwarestandardBackwardcompatiblewithMXI-1TECHNOLOGYPCIeXtensionsforInstrumentsPCInstruments

Advantages

LowCostAvailability

Disadvantages

NoInstrumentbussesLimitedNo.ofslotsNoCoolingExternalConnectionsGPIBAdvantagesDesignedforInstrumentControlRuggedConnectorsAvailabilityNosizerestrictionsDisadvantagesLimitedtriggeringSlowWhatisPXI?PXIisanOpenStandarddefining:MechanicalRequirementsElectricalRequirementsSoftware/OperatingSystemRequirementsIntroducedbyNIin1997AdoptedasanIndustry-Standardin1998Rev2.0ofthePXISpecificationreleasedin2000PXIUsesStandardTechnologyCompactPCIThePXIsystemspecificationextendsCompactPCIforInstrumentation.CompactPCICombines...PCIelectricalspecificationEurocardmechanicalspecificationsLatestconnectortechnologiesPCIEurocardpackagingIECconnectorsCompactPCIACloserLookatPXISoftwareElectricalMechanicalMechanicalFeaturesMechanicalChassisMechanicalMechanicalFeaturesModular,rugged,shockresistantPXIaddsActiveCoolingPXIrequiresTemperatureRatingsPXIdefinescontrollertobeonleftMechanicalFormFactors64-bitPCIandPXIFeatures3UPXIJ1J232-bitPCI6UPXIJ5J4J3J2J164-bitPCIandPXIFeatures32-bitPCIPXIReservedPXIReservedPXIReservedMechanical100×160mm233.35×160mm3U&6UInteroperability6U3U3UJ1J2J3J4J5MechanicalRuggedConnectorsHighPinCountImpedanceMatchedReliableKeyedMechanicalInteroperabilitywithCompactPCIMechanicalElectricalArchitecturePCI(PeripheralComponentInterconnect)Features33/66MHzperformance32-bitand64-bitdatatransfers132Mbytes/s(32-bit,33MHz)to528Mbytes/s(64-bit,66MHz)peakdataratesSystemexpansionviaPCI-PCIbridges3.3VmigrationPlugandPlaycapabilityPXIHardwareExtensions10MHzReferenceClockStarTriggerLocalTriggerLocalBus10MHzReferenceClockAvailableonallperipheralslotsAccurateClockforreferenceAllowssynchronisationofperipheralsCanbesubstitutedforexternalClockStarTriggerDedicatedtriggertoeachperipheralslot(max13)Accuratetiming(<1nsskew)TriggerBus8SignalsCommontoallslotsinasinglePCIsegmentCanbebridgedacrosssegmentsLocalBus13SignalLinesDigitalorAnalogSignalsConnectsAdjacentSlotsCanbeusedtodaisy-chainperipheralsTriggerBusElectricalFeaturesSystemControllerStarTriggerControllerPeripheralPeripheralPeripheral10MHzCLK132Mb/s,33MHz,32-bitComputerBusStarTriggerElectricalLocalBusSystemExpansionwithPCI-PCIBridgeTechnologyTwoBusSegmentsoffers13expansionslots(2bussegments)x(8slotspersegment)-(1systemcontrollerslot)-(2slotsforPCI-PCIBridge)=13availableexpansionslotsExampleTypicalPC3PCISlotsPXIChassis(1Segment)7PXISlotsPXIChassis(multi-Segment)7PXISlots+6foreachsegmentSoftwareFeaturesControllersMUSTSupportaSWFramework:

-WindowsNT

-Windows95PeripheralsMUSTbesuppliedwithaWIN32DeviceDriver.SoftwareSoftwareFeaturesVISA

(VirtualInstrumentSoftwareArchitecture)-RS232-GPIB-VXI-PXIOtherrequirementsOverviewUsesPC

SWandHWTechnology:

-LowCost

-HighPerformance

-EaseofUseModular,RuggedFormFactorwithmoreslotsBuilt-inInstrumentationFeaturesPXIWorksTogetherwithOtherStandardsMXIGPIBVXIorVMEStand-aloneInstrumentPXISystemModulesModulesCompactPCIEmbeddedControllerMultisystemExtensionInterfaceforPXIandCompactPCIMXI-3ImplementationofPCI-PCIBridgeHundredsofPXI/CompactPCIProducts

areAvailableTodaySCSIEthernetPCMCIACANDeviceNETRS-232,RS-485MultifunctionI/OHigh-SpeedDigitalI/OImageAcquisitionIP,PMC,PC-MIPCarriersOscilloscopesDigitalMultimetersSerialDataAnalyzersMXI-2KitsforVXI/VMEGPIBSwitchMultiplexersMotionControlReceiverInterconnectDevicesDigitalSignalProcessingPXIBenefitsAttributeAdvantageSizeSmallerphysicalsizethanVXIorGPIBThroughputSignificantlyfasterthanGPIBorVXIArchitectureOpen,well-definedindustrystandardConstructionRuggedconstruction,suitableforbench,rack-mountandportableapplicationsAvailabilityNumerouschassisaswellasanalog,digital,andswitchinginstrumentsavailablefrommultitudeofvendorsPriceSignificantcostadvantageoverGPIBandVXINowmorethan60membersPromotePXIEnsureInteroperabilityMaintainandcontrolthePXISpecification

LaboratoryVirtualInstrumentEngineeringWorkbenchGraphicalProgrammingEasytouseFasterDevelopmentTimeGraphicalUserInterfaceGraphicalSourceCodeEasilyModularizedAcquisitionwithLabVIEWGPIBSerialDataAcquisition(DAQ)RemoteDataAcquisition(RDA)PXIImageAcquisition(IMAQ)MotionControlReal-Time(RT)BoardPLCAcquireAnywhereAnalyzeAnywhereAnalysiswithLabVIEWAnalysisVIsforDifferentialEquations,Optimization,CurveFitting,Calculus,LinearAlgebra,Statistics,etc.SignalProcessingVIsforFiltering,Windowing,Transforms,PeakDetection,HarmonicAnalysis,SpectrumAnalysis,etc.PresentAnywherePresentationwithLabVIEWPresentationwithLabVIEWcanbedoneonyourPCoroveranetwork,andyoucanusethirdpartysoftwarelikeExcelEquipmentNeededforthisCourseComputerrunningLabVIEWGPIBBoardandCableNIInstrumentSimulatorSerialCableDAQBoardandCableDAQSignalAccessoryUseLabVIEWtocreateyourapplicationsUsevariousdebuggingtechniquesUnderstandfrontpanels,blockdiagrams,andicons/connectorsUsebothbuilt-inLabVIEWfunctionsandlibraryVIsCreateandsaveyourownVIssoyoucanusethemassubVIsCreateapplicationsthatuseplug-indataacquisition(DAQ)boardsCreateapplicationsthatuseGPIBandserialportinstrumentsCourseGoalsWhatavirtualinstrument(VI)isTheLabVIEWenvironmentLesson1

IntroductiontoLabVIEWFrontPanelControls=InputsIndicators=OutputsBlockDiagramAccompanying“program”forfrontpanelComponents“wired”togetherVirtualInstruments(VIs)

AniconrepresentsaVIinotherblockdiagramsAconnectorpassesdatatoandreceivesdatafroma“subVI”throughterminalsiconconnectorterminalsIcon/ConnectorExample:TemperatureVILabVIEWStartupScreenPanelWindowPanelToolbarIconPaneDigitalControlFreeLabelKnobOwned

LabelKnobControlChartLegendChartWireDataChartTerminalSubVIForLoopStructureDigitalControlTerminalMultiplyFunctionNumericConstantKnobTerminalTimingFunctionDiagramWindowStatusToolbarRunbuttonContinuousRunbuttonAbortbuttonPause/ContinuebuttonFontringAlignmentringDistributionringReorderringMenusPullDownMenusLoading/SavingVIsUsetoLoadVIsUsetoSaveVIsToolsPaletteOperatingToolPositioning/ResizingToolLabelingToolWiringToolPop-UpMenuToolScrollingToolBreakpointToolProbeToolColorCopyingToolColoringToolEditingandDebuggingToolsFloatingPaletteControlandFunctionPalettesGraphical,floatingpalettesSubpalettescanbeconvertedtofloatingpalettesControlsPalette(PanelWindow)FunctionsPalette(DiagramWindow)SummaryVirtualinstruments(VIs)havethreemainparts:thefrontpanel,theblockdiagram,andtheicon/connectorThefrontpanelistheuserinterfaceofaLabVIEWprogramandtheblockdiagramistheexecutablecodeFloatingPalettesToolsPaletteControlsPalette(onlywhenPanelWindowisactive)FunctionsPalette(onlywhenDiagramWindowisactive)Lesson2

Creating,Editing&DebuggingaVIHowtoCreateVIsHowtoEditVIsHowtoDebugVIsCreatingaVIFrontPanelNumericcontrolsandindicatorsBooleancontrolsandindicatorsConfiguringcontrolsandindicatorsUsepop-upmenusPartshavedifferentmenusDigitalControlDigitalIndicatorLabelsIncrementButtonsBooleanControlBooleanIndicatorAccessingPop-UpMenusPopuponthelabelforitspop-upmenu.Popuponthedigitaldisplayforitspop-upmenu.CreatingaVIBlockDiagramTerminalpatternfortheAddFunctionandtheSubtractfunction(threenodeterminals).NodesWiresControlTerminalsDiagramWindowPanelWindowIndicatorTerminalsWiringaVIBlockDiagramScalar1DArrayNumericBooleanStringOrange(floatingpoint)Blue(integer)GreenPurple2DArrayDataflowProgrammingBlockdiagramdoesNOTexecutelefttorightNodeexecuteswhendataisavailabletoALLinputterminalsNodessupplydatatoalloutputterminalswhendoneDemonstrateDataFlowEditingTechniquesCreatingObjectsfromDiagramWindowSelectingObjectsDeletingObjectsUndoandRedoFreevs.OwnedLabelsWiringTechniquesChangingFontsandTextColorsCopyingObjectsUsingColorDebuggingTechniquesFindingErrorsExecutionHighlightingClickonbrokenRunbuttonWindowshowingerrorappearsClickonExecutionHighlightingbutton;dataflowisanimatedusingbubbles.Valuesaredisplayedonwires.DebuggingTechniquesProbeBreakpointsSelectBreakpointtoolfromToolspaletteandclickonwireornodewhereyouwantexecutiontopauseRight-clickonwiretodisplayprobeanditshowsdataasitflowsthroughwiresegmentYoucanalsoselectProbetoolfromToolspaletteandclickonwireSummaryTwowindowstocreateaVI--FrontPanelandBlockDiagram

Controlterminalshavethickerbordersthanindicatorterminals.AllLabVIEWobjectshavepop-upmenusWiringMechanismtocontroldataflowandproduceLabVIEWprogramsBrokenRunarrow=nonexecutableVIVariousdebuggingtoolsandoptionsavailablesuchassettingprobesandbreakpoints,executionhighlighting,andsinglesteppingLesson3

CreatingaSubVIWhataSubVIis.Howtocreatetheiconandconnector.HowtouseaVIasasubVI.SubVIsMeansofusingaVIintheblockdiagramofahigher-levelVI•RequiresiconandconnectorSubVIExample–CalculatingSlopeCreatingtheIconPopupintheiconpane(PanelorDiagram)AlwayscreateblackandwhiteiconCreatingtheConnectorPopupintheiconpane(Panelonly)CreatingtheConnector.ClickTheConnectorPaneTheterminalcolorsmatchthedatatypestowhichtheyareconnectedClickontheterminaltoseeitsassociatedfrontpanelobjectUsingtheVIasaSubVIChangesmadetosubVIsavedinmemoryuntilsavedtodisk

CallingsubVIsFunctions>>SelectaVI…ORDragiconontotargetdiagramSummaryVIscanbeusedassubVIsafteryoumake: –Icon –ConnectorIconcreatedusingIconEditorConnectordefinedbychoosingnumberofterminals LoadsubVIsusingtheSelectaVI...optionintheFunctionsmenuordraggingtheiconontoanewdiagramLesson4

LoopsandChartsWhileLoopsWaveformchartsShiftregistersForLoopsWhileLoopDo(ExecutediagraminsideLoop)WhileConditionisTRUE1.SelectWhileLoop2.Enclosecodetoberepeated3.DropordragadditionalnodesandthenwireWhileLoopSelecttheLoopConditionRight-clickonConditionalTerminaltodefinewhentheloopstopsIterationTerminalConditionalTerminalWaveformCharts•SelectedfromtheControls>>GraphsubpaletteCustomizingChartsandGraphsDemonstrateuseoftheChart/GraphpaletteonthecomputerLockswitchSinglefitbuttonZoombuttonReturntostandardmodeScalemarkerformattingPanbuttonX-axisControlsY-axisControlsDigitaldisplays(fromShowmenu)Scrollbars(fromShowmenu)Customizetheaxes(fromFormatting…inpop-upmenu)Zoomingcontrols(onpalette)WiringtoCharts•Single-PlotChartShiftRegisters•Availableatleftorrightborderofloopstructures•PopuponborderandselectAddShiftRegister•LeftterminalprovidesstoreddataatbeginningofnextiterationRightterminalstoresdataoncompletionofiterationBeforeLoopBeginsFirstIterationSecondIterationLastIterationInitialValueValue1Value1Value2Value2Value3Value3InitialValueInitializingShiftRegistersRUN1RUN2InitialValue=5InitializedUninitializedInitialValue=5InitialValue=0InitialValue=8ForLoop•InStructuressubpaletteofFunctionspalette•Enclose