第四章静态功耗优化技术课件

第四章多电压域设计技术

（Multi-VoltageDomain）4.1多电压域设计

VLSI发展的一个重要趋势是SOC工艺的进步使SOC成为可能；

设计复杂度的提高需要新的设计方法SOC中各部分性能要求不尽相同，可工作在不同电压下，性能要求高的工作的高电压域，反之。。。

同一部分根据其工作负荷也可工作在不同电压工作电压可以有不同变化方式•StaticVoltageScaling(SVS):differentblocksorsubsystemsaregivendifferent,fixedsupplyvoltages.（最简单的多电压域设计）•Multi-levelVoltageScaling(MVS):anextensionofthestaticvoltagescalingcasewhereablockorsubsystemisswitchedbetweentwoormorevoltagelevels.Onlyafew,fixed,discretelevelsaresupportedfordifferentoperatingmodes.•DynamicVoltageandFrequencyScaling(DVFS):anextensionofMVSwherealargernumberofvoltagelevelsaredynamicallyswitchedtofollowchangingworkloads. •AdaptiveVoltageScaling(AVS):anextensionofDVFSwhereacontrolloopisusedtoadjustthevoltage.

就是最简单的multi-voltage设计（SVS）也给设计增加了难度

•Levelshifters.Signalsthatgobetweenblocksthatusedifferentpowerrailsoftenrequirelevelshifters•CharacterizationandSTA.Withasinglesupplyfortheentirechip,timinganalysiscanbedoneatasingleperformancepoint.Thelibrariesarecharacterizedforthispoint,andthetoolsperformtheanalysisinastraight-forwardmanner.Withmultipleblocksrunningatdifferentvoltages,andwithlibrariesthatmaynotbecharacterizedattheexactvoltageweareusing,timinganalysisbecomesmuchmorecomplex•Floorplanning,powerplanning,grids.Multiplepowerdomainsrequiremorecarefulanddetailedfloorplanning.Thepowergridsbecomemorecomplex.•Boardlevelissues.Multi-voltagedesignsrequireadditionalresourcesontheboard–additionalregulatorstoprovidetheadditionalsupplies.•Powerupandpowerdownsequencing.Theremaybearequiredsequenceforpoweringupthedesigninordertoavoiddeadlock.•高电压电源推低电压单元一般不会有问题但时序参数不准，因库单元的时序参数是针对同电位的驱动和接收电路的，驱动端过驱动的时序最好专门单元4.2LevelShifter•低推高时会出现P、N管同时导通，必须用LevelShifterSuch“up-shifting”levelconvertersrequiretwosupplyrails–andtypicallyshareacommonground.Thewellstructurescannotbejoinedtogetherbutmustbeassociatedwiththesuppliesindependently.•高推低时，LevelShifter使用低电压，故一般放在低电压域，因其使用低电压4.3LevelShifterPlacement•两电压域的模块距离较远时，可插入Buffer，BUFFER使用高电压•低推高时，LevelShifter一般放在高电压域，但因其使用高、低两个电压，低压要象信号线一样连出Sincetheoutputdriverrequiresmorecurrentthantheinputstage,weplacethelevelshifterinthe1.2Vdomain.placingthelevelshiftersinthedestinationdomain•ClockSkew静态时序分析：都要针对多电压域进行4.4多电压设计时的时序问题第五章漏电流控制技术ThePowerCrisisfromIntelLeakagePoweriscatchingupwiththeactivepowerinnano-scaledCMOScircuits.ThePowerCrisisfromIBM低压设计的问题：漏电流为什么要低电压设计？小尺寸器件的要求漏端热载流子退化临界电场Em<0.2MV/cm0.35um击穿电压6V左右一般要求工作电压为击穿电压的1/3~1/2一般按恒定电场ScaleDown低功耗设计的要求5.1Low-VoltageLow-Threshold-VoltagecircuitDesignPNReverse-BiasCurrent(I1)WeakInversion(I2)（亚域电流）Gate-InducedDrainLeakage(I3)GateOxideTunneling(I4)5.2漏流主要来源PowerGatingStackedCMOSDual（Multi)ThresholdCMOS5.3LeakageControlTechniques一、PowerGating技术

1、Power-Gating与Clock-GatingClockGatingPowerGatingClock-Gating只关断时钟，节省动态功耗，静态功耗不变。Power-Gating是关断电源，动态、静态功耗都不存在（还存在开关管的漏电）2、PowerGating的适用性、问题及解决的途径概述powergatingismoreinvasivethanclock-gatinginthatitaffectsinter-blockinterfacecommunicationandaddssignificanttimedelaystosafelyenterandexitpowergatedmodes.Shuttingdownpowertoablockoflogicmaybescheduledexplicitlybycontrolsoftwareaspartofdevicedriversoroperatingsystemidletasks.Alternativelyitmaybeinitiatedinhardwarebytimersorsystemlevelpowermanagementcontrollers.Inanyevent,wearefacedwitharchitecturaltrade-offsbetween•theamountofleakagepowersavingsthatispossible•theentryandexittimepenaltiesincurred•theenergydissipatedenteringandleavingsuchleakagesavingmodes•theactivityprofile(proportionandfrequencyoftimesasleeporactive)AcachedCPUsubsystemcantypicallybedormantorinactiveforlongperiods,makingpowergatingattractive.Buttherearesometrade-offsthatmustbeconsidered:•PowergatingtheentireCPUprovidesverygoodleakagepowerreduction.Butwake-up-timeresponsetoaninterrupthassignificantsystemleveldesignimplications.•IfthecachecontentsarelosteverytimetheCPUispowereddownthenthereislikelytobeasignificanttimeandenergycostinallthebusactivitytorefillthecachewhenitispoweredup.•Thenetenergysavingsdependonthesleep/wakeactivityprofileastohowmuchenergywassavedwhenpowergatedversustheenergyspentinreloadingstate.AperipheralsubsystemmayhaveamuchbetterdefinedprofilethanaCPU.Buttherearestillsometrade-offs.Inparticular,itmaybenecessarytorestorestatequicklyonwake-uptomaximizepowersavings:•Thedevicedrivermayberequiredtoexplicitlyload/restorekeystateorinitiatehardwaresequencercontrolaspartofthesleep/wakeupsequence,butthisplacesasignificantburdenonsoftware.•Abetterapproachmaybefortheperipheraltostorekeystateinternallyduringsleepmode,butthisrequiresspecialcircuitryandadditionalcontrol.multi-processorCPUclusterwhereoneormoreprocessorsmaybepowergatedoffcompletely.Inthiscaseweassumethataprocessorispowereddownonlywhenithascompletedataskandisidle,waitingforanothertasktobeassigned:•PowergatingindividualCPUsprovidesverygoodleakagepowerreduction.•BecausetheCPUhascompleteditstask,thefactthatthelocalcachecontentsarelostwhenitispowergatedisnotaproblem.TheCPUisawokencleanandresetreadytoexecuteandcachethenexttaskitisgiven.•OptimizedenergysavingsmaywellrequireadaptiveshutdownalgorithmsthatvarythenumberofCPUcorespowergatedandactivewithvaryingworkload.3、PowerGating的实现externallyswitchedpowersupply：长期闲置Internalpowergating：短期闲置PowerGating的设计涉及到Thecriticalissuesinpowergatinginclude：switchingnetworkandthepowergatingcontroller.isolationcells.retentionflops开关网络的设计：

开关网络的设计应避免多层次PowerGating（避免IRDrop增大）开关网络可以是“header”switch；也可以是“footer”switch或Both（IRDrop大，代价大），一般用其一。大多用“header”

Withaheader-styleswitchfabric,theinternalnodesandoutputsofapowergatedblockcollapsedowntowardsthegroundrailwhentheswitchisturnedoff.Withafooter-styleswitchfabrictheinternalnodesandoutputsallchargetowardsthesupplyrailwhentheswitchisturnedoff.Notethathereisnoguaranteethatthepowergatednodeswilleverfullydischargetogroundorfullychargetothesupply.Instead,anequilibriumisreachedwhentheleakagecurrentthroughtheswitchesisbalancedbythesub-thresholdleakageoftheswitchedcells.ThisisoneofthereasonswhyisolationcellsarerequiredonoutputsofpowergatedblocksSwitchVddorVssratherthenbooth,inordertominimizetheIRdrop.Decideearlyoninthedesignphasewhetherheaderorfooterswitchesmostnaturallyfitwiththesystemdesign.Headerswitchesmaybethemostappropriatechoiceforswitchesifexternalpowergatingwillalsobeusedonthechip.Headerswitchesmaybethemostappropriatechoiceforswitchesifmultiplepowerrailsand/orvoltagescalingwillbeusedonthechip.（共地）Akeyconcernincontrollingtheswitchingfabricistolimitthein-rushcurrentwhenpowertotheblockisswitchedon.Excessivein-rushcurrentcancausevoltagespikesonthesupply,possiblycorruptingregistersinthealways-onblocks,aswellasretentionregistersinthepowergatedblockOnerepresentativeapproachistodaisy-chainthecontrolsignaltotheswitches.Thecontrolsignalfromthepowercontrollerisconnectedtothefirstswitch,anditbuffers(withanappropriatedelay)thesignalandsendsitontothenextswitch.Turningontheswitchingfabricistouseseveralpower-upcontrolsignalsinsequence.Thefirstcontrolsignalmayturnonasetofweakor“trickle”switches,whichinitiatethepowerupbutlimitthein-rushcurrent.Thesecondcontrolsignalmaythenturnonthemainsetofpowerswitches.Theseswitcheshavemultipleenablepins;typically,thesmallerswitchisturnedonfirsttogetthevoltageupto95percent,thenthebiggerswitchisturnedontoreducetheIRdrop.Power-Gating的粒度（粗粒度）Incoarsegrainpowergating,ablockofgateshasitspowerswitchedbyacollectionofswitchcells.Thesizingofacoarsegrainswitchnetworkismoredifficultthanafinegrainswitchastheexactswitchingactivityofthelogicitsuppliesisnotknownandcanonlybeestimated.Butcoarsegraingatingdesignshavesignificantlylessareapenaltythanfinegrain.多数应用：粗粒度Power-Gating的粒度（细粒度）Infinegrainpowergatingtheswitchisplacedlocallyinsideeachstandardcell.Sincethisswitchmustsupplytheworstcasecurrentrequiredbythecell,ithastobequitelargeinordernottoimpactperformance.Theareaoverheadofeachcellissignificant(often2x-4xthesizeoftheoriginalcell).ThekeyadvantageoffinegrainpowergatingisthatthetimingimpactoftheIRdropacrosstheswitchandthebehavioroftheclampareeasytocharacterizeastheyarecontainedwithinthecell.ThismeansthatitisstillpossibletouseatraditionaldesignflowtodeployfinegrainpowergatingIsolationCell的设计模块被PowerDown后输出浮空，电平未知，被其驱动的负载可能处于P、N管都通的情况需加信号隔离，输出固定值隔离单元输出一般为被驱动的无效态增加隔离单元增加了延迟选用上下拉做隔离可消除延迟但隔离信号处于多源驱动，Power-gatingcontroler设计时必须注意，避免出现多源竞争用OR还是AND要看被驱动电路输入是高有效还是低有效。若某输入为低时发出中断，在需用OR将其启动为高因驱动负载可能是多个，故信号隔离单元一般亦放在驱动端SignalIsolation应满足一定时序要求

StateRetention设计Givenapowerswitchingfabricandanisolationstrategy,itispossibletopowergateablockoflogic.Butunlessaretentionstrategyisemployed,allstateinformationislostwhentheblockispowereddown.Toresumeitsoperationonpowerup,theblockmusteitherhaveitsstaterestoredfromanexternalsourceorbuildupitsstatefromtheresetcondition.Ineithercase,thetimeandpowerrequiredcanbesignificant.Retentionregisterstypicallyhaveanauxiliaryorshadowregisterthatisslowerthanthemainregisterbutwhichhasmuchlessleakagecurrent.Theshadowregisterisalwayspoweredup,andstoresthecontentsofthemainregisterduringpowergatingTheseretentionregistersneedtobetoldwhentostorethecurrentcontentsofthemainregisterintotheshadowregisterandwhentorestorethevaluebacktothemainregister.Thiscontrolisprovidedbythepowergatingcontroller.

StateRetentionandRestorationMethodsAsoftwareapproachbasedonreadingandwritingregistersAscan-basedapproachbasedonusingscanchainstostorestateoffchipAregister-basedapproachthatusesretentionregisters

StateRetention时序SRPG不能断电（VRET）SRPG速度可以慢，漏流要小实现Power-Gating应解决如下问题•Designofthepowerswitchingfabric•Designofthepowergatingcontroller•Selectionanduseofretentionregistersandisolationcells•Minimizingtheimpactofpowergatingontimingandarea.•Thefunctionalcontrolofclocksandresets•Interfaceisolation实现Power-Gating应解决如下问题•Developingthecorrectconstraintsforimplementationandanalysis•Performingstate-dependentverificationforeachsupportedpowerstate•Performingpowerstatetransitionverificationtoensurealllegalstateentryandexitarcsaresimulatedandverified•Developingastrategyformanufacturingandproductiontest一个完整的PowerGating的设计switchingnetworkisolationcellsretentionflopspowergatingcontrollerLevelShifter（看是否是多电压域）

PowerCycleSequenceForpower-down,aspecificsequenceisgenerallyfollowed:isolation,stateretention,powershut-off(见下图).Forthepower-upcycle,theoppositesequenceneedstobefollowed.Thepower-upcyclecanalsorequireaspecificresetsequence.4、CadenceLow-PowerFlowersCPF（CommonPowerFormat）是Cadence提出，SiliconIntegrationInitiative通过的标准CPF-basedflow中RTL不需修改;TheRTLcanbeinstantiatednnumberoftimes,andeachinstancewillhaveadifferentlow-powerbehaviorasspecifiedbythecorrespondingCPF.

如何利用CPF描述电源管理方案设计还是按原来的方法进行，电源管理方案由CPF描述图中pdA，pdB可以Power-Down，其他部分省缺属于pdTop电压域及Power-Down条件描述#Definethetopdomainset_designTOP#Definethedefaultdomaincreate_power_domain\–namepdTop–default#DefinePDAcreate_power_domain\–namepdA\–instances{uAuC}\–shutoff_condition{!uPCM/pso[0]}#DefinePDB–PSOwhenpsoislowcreate_power_domain–namepdB\–instances{uB}\–shutoff_condition{!uPCM/pso[1]}

隔离和stateretention描述#ActivehighIsolationsethiPin{uB/en1uB/en2}create_isolation_rule\–nameir1\–frompdB\–isolation_condition{uPCM/iso}\–isolation_outputhigh\–pins$hiPin#DefineState-Retention(SRPG)setsrpgList{uB/reg1uB/reg2}create_state_retention_rule\–namesr1\–restore_edge{uPCM/restore[0]}\-instances$srpgList

Level-Shifter描述#DefineLevel-Shiftersinthe#“to”domaincreate_level_shifter_rule–namelsr1\–to{pdB}–from{pdA}create_level_shifter_rule–namelsr2\–to{pdA}–from{pdB}create_level_shifter_rule–namelsr3\–to{pdTop}–from{pdB}create_level_shifter_rule–namelsr4\–to{pdA}–from{pdTop}CPF支持VLSI设计全流程用RTL完成功能设计用CPF完成PowerIntent描述CPF语法，RTL与CPF的相容性，CPF的完整性等低功耗模式下的验证。如：模块电源关闭、重启，保持寄存器等含CPF进行逻辑综合，对DVFS需多约束文件。isolationandstateretention的插入使等价性检查更复杂减小测试功耗isolation、stateretention、Level-Shifer等单元的测试powerswitchinsertionPowerdomain–awareplacementandoptimization等等Power-down模拟下的逻辑模拟逻辑综合左上窗口未含CPF•Isolationcellstoalloutputsofpowerdomains•Isolationcellstoinputswherespecified•Levelshifterstosignalscrossingvoltagedomains•ReplacementofallflopswithretentionflopswherespecifiedTestForLow-PowerTestForLow-Power

VT=√2εε0qNA(2ψB+VBS)/Ci+2ψB+φms－Qf/Ci

.二、晶体管堆叠技术衬底电压Vbb是如何影响Vth的？N管P形衬底加负电压时Vth升高、加正偏压时Vth降低P管N形衬底加正电压时Vth升高、加负偏压时Vth降低Vs>0时VG＝0相当于VGS＝－Vs结论串联堆叠管越多漏流越小不通的管子位置越低（靠近地）漏流越小插入高Vth管对降低漏流大有好处原因ZLa(kT)22q2

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