第二章CMOS制备基本流程

2.1

CMOS制造工艺流程简介

We

will

describe

a

modern

CMOS

process

flow.Process

described

here

requires

16

masksand

>

100

process

steps.1第二章CMOS制备基本流程第一页，共三十八页。StagesofICFabrication2第二页，共三十八页。•Inthe

simplest

CMOS

technologies,

weneed

to

realizesimply

NMOSandPMOStransistorsforcircuits

likethoseillustratedbelow.CMOSDigital

Gates反相电路或非门：同时输入低电平时才能获得高电平输出3第三页，共三十八页。PMOSand

NMOSwafer

crosssectionafterfabrication2-LevelMetal

CMOS两层互连布线的CMOS4有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。第四页，共三十八页。••••••••Choosing

a

SubstrateActiveRegionNand

P

WellGateTip

or

ExtensionSource

and

DrainContactand

Local

InterconnectMultilevel

MetalizationProcessing

Phases5第五页，共三十八页。1µmPhotoresist40

nmSiO2Choose

the

substrate(type,

orientation,resistivity,

wafer

size)•

Initial

processing: -

Wafer

cleaning -

thermal

oxidation,

H2O

(≈

40

nm,

15

min.

@

900ºC) -

nitride

LPCVD(低压化学气相沉积)

(≈

80

nm@

800ºC)•

Substrate

selection:-moderately

high

resistivity(25-50

ohm-cm)-(100)

orientation-P-

type.80

nmSi3N4Choosinga

SubstrateSi,(100),PType,25~50Ωcm1st

Mask

Photoresist

•

spinning

and

baking@

100ºC(≈

0.5

-

1.0

µm)62.2有源区的形成第六页，共三十八页。•

Photolithography-Mask

#1

pattern

alignmentand

UV

exposure-Rinse

away

non-pattern

PR-Dry

etch

the

Nitride

layer--Plasma

etch

with

FluorineCF4

or

NF4

Plasma-Strip

Photoresist(H2SO4或O2plasma)ActiveAreaDefinition(主动区)SiO2Si3N4Photoresist7第七页，共三十八页。•Wet

Oxide

(thickSiO2)-

H2O

(≈500

nm,90min.

@1000ºC)•

StripNitridelayer

-Phosophoricacid(磷酸)

orplasma

etch，选择性问题FieldOxideGrowth

-LOCOS:

Local

Oxidation

ofSilicon(局部硅氧化工艺)SiO2Si3N4•

薄的SiO2层，厚的Si3N4层，避免鸟喙(bird’sbeak)的影响8•场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。第八页，共三十八页。•

Photolithography(套刻)-Mask#2

patternalignmentandUVexposure•

IonImplantation离子注入

-

B+

ion

bombardmentPenetrate

thin

SiO2

and

fieldSiO2

--反型：半导体表面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。-

150-200keVfor1013cm-2

--Implantation

Energy

andtotaldose

adjusted

fordepth

and

concentrationP-wellFabrication•

StripPhotoresist-Rinseawaynon-patternPR2.3N阱和P阱的形成SiO2Photoresist9第九页，共三十八页。•IonImplantation

-

P+

ionbombardment-

PenetratethinSiO2

and

field

SiO2-

300-400keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjustedfordepthand

concentration•

Strip

PhotoresistN-well

Fabrication•

Photolithography

-Mask#3

patternalignmentand

UV

exposure-

Rinse

away

non-patternPR10第十页，共三十八页。•

ThermalAnneal(热退火)-Repair

crystal

lattice

structuredamagedue

toimplantation•

DryFurnace(N2

ambient，防止氧化层生成)

-Anneal30

min@

800˚C

orRTA(快速热退火)10

sec@1000˚C-

Drive-in4-6

hours

@1000

˚C-1100˚CThermalAnnealand

Diffusion•NandPDrive-in(扩散推进)-

Thermaldiffusionof

dopant

toshallower

thandesired

depth--

Drive-inisa

cumulativeprocess!11第十一页，共三十八页。•

Photolithography

-Mask

#4patternalignmentand

UV

exposure-

Rinseawaynon-patternPR-B+ion

bombardment-50-75keV

for1-5×

1012cm-2--

ImplantationEnergyand

totaldoseadjustedfor

depth

andconcentration•

Strip

PhotoresistThresholdAdjustment,

P-typeNMOS•

Ion

Implantation2.4栅电极的制备开启电压调整12调整之前P阱的掺杂浓度调整时的注入剂量第十二页，共三十八页。Threshold

Adjustment,N-typePMOS•

Photolithography

-

Mask

#5

pattern

alignmentand

UVexposure-Rinse

awaynon-patternPR-

As+

ion

bombardment-

75-100keV

for

1-5×

1012cm-2--

ImplantationEnergy

and

total

dose

adjusted

for

depthand

concentration•Strip

Photoresist•Ion

Implantation13第十三页，共三十八页。•

Remove

existing

gate

regionoxide•

Furnace

Steps -

ThermalAnneal-

Oxide

growth3-5nm--O2

ambient--0.5-1hour@800°CGateOxide

Growth栅极氧化层生长-HF

etch，具有良好的选择性--DryFurnace(N2

ambient)--30min@

800˚C14第十四页，共三十八页。•LPCVD

Deposition

of

Si-

Silane硅烷•Amorphous

or

polycrystalline

silicon

layer

results

Ion

Implantation -

P+

orAs+

(N+)

implantdopes

thepoly(typically

5

×

1015cm-2)

PolysiliconGate

Deposition•

0.3-0.5

umSiO2多晶硅薄膜15热分解第十五页，共三十八页。•

Photolithography

-

Mask#6patternalignmentand

UVexposure•Plasma

Etch

-

Anisotropic

etch各向异性蚀刻

--

Vertical

etch

rate

high

--

Lateral

etchrate

lowGate

Patterning（栅极的图形化）-Rinseaway

non-patternPR•

Clorine(氯)orBromine(溴)based

forSiO2

selectivity16第十六页，共三十八页。目标：NMOS器件中的N-注入区PMOS器件中的P-注入区多晶硅栅的两侧形成侧壁隔离层的薄氧化层2.5前端或延伸区(LDD)的形成17第十七页，共三十八页。LDD:•Lightly

Doped

Drain(轻掺杂漏)•

Reduce

shortchanneleffectsdue

to

gate

voltagemagnitudesandelectric

fields•

Source

and

Drain

mustbelayeredasNMOS:N+N-P

orPMOS:P+P-NExtension

(LDD)

Formation

NMOS•Photolithography

-

Mask#7

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR-P+

ionbombardment-50keVfor

5

×

1013cm-2•

Strip

Photoresist•Ion

Implantation18第十八页，共三十八页。•Photolithography

•Mask

#8pattern

alignment

andUV

exposure

•

Rinse

away

non-patternPR•

IonImplantation

•

B+ionbombardment

•50keV

for

5×

1013cm-2•StripPhotoresistExtension(LDD)

FormationPMOS19第十九页，共三十八页。SiO2

隔离介质层CVDorLPCVDDepositionofSiO2•SilaneandOxygenOr0.5um•Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition20第二十页，共三十八页。•

Photolithography •Mask

#6

oversizedpattern

alignment

and

UV

exposure

•

Rinse

away

non-pattern

PR•

Verticaletchratehigh•

Lateraletch

ratelow•StripPhotoresistAnisotropic

Spacer

Etch•

Plasma

Etch •Anisotropic

etch•

Flourine

based21第二十一页，共三十八页。•

ScreenOxideGrowth•

ThinSiO2layer

~10

nm

toscattertheimplanted

ions•

Photolithography•

Mask#9patternalignment

and

UVexposure•

Rinse

awaynon-patternPR•IonImplantation •

As+

ion

bombardment

•

75

keVfor

2-4×1015cm-2•Strip

PhotoresistNMOS

Sourceand

Drain

Implant2.6源漏区的形成Arsenic•

Reduce

channeling22第二十二页，共三十八页。•Photolithography•Mask#10

pattern

alignment

andUV

exposure•

Rinseaway

non-pattern

PR•

IonImplantation

•

B+ion

bombardment •

5-10keVfor

1-3

×1015cm-2

•StripPhotoresistPMOS

Sourceand

Drain

Implant23第二十三页，共三十八页。•

N+

andP+Drive-in•Thermaldiffusion

ofdopant

toshallowerthan

desired

depth

•Drive-inisa

cumulativeprocess!•DryFurnace(N2

ambient) •

Anneal30

min@

900˚C

orRTA

60

sec

@

1000

˚C

-

1050

˚CTransient

Enhanced

Diffusion

(TED瞬态增强扩散)

•Higher

than

normal

diffusivity

due

tocrystal

damageThermal

Annealing•ThermalAnneal•Repaircrystallatticestructuredamageduetoimplantation24第二十四页，共三十八页。2.7接触与局部互联的形成

Contactsand

Interconnects•Titaniumsputteringlocalcontacts•ConformalCoatwithSiO2•Planarization•TungstenPlugvias•AluminumMetalDeposition•Repeat–Coat–Planarize–Plug–Metaldeposition25第二十五页，共三十八页。•

HF

etchtoremovethin

SiO2 •Remove

screenoxidefromdrain,

source

and

ploy

gateregions •

Dip(浸)for

afewsecondswithHFContactOpeningsLDDandSidewallstructure•NMOS:LateralN+N-PN-N+•PMOS:LateralP+P-NP-P+26第二十六页，共三十八页。

TitaniumDeposition•

Ti

isdepositedbysputtering(typically

100

nm).

•

Titarget

hitwithAr+

ionsin

avacuum

chamber•The

Ti

is

reactedinanN2

ambient•

FormsTiSi2

andTiN(typically1min

@600-700

˚C).•

TiSi2

has

excellentcontactcharacteristics(良好的导体)•

TiNdoes

not,

but

canbeused

forlocal

wiring(导电材料，短程互连布线)TiSi2TiN27第二十七页，共三十八页。•Photolithography•Mask#11patternalignmentandUV

exposure•

Rinseawaynon-pattern

PR•

TiN

etch

•

NH4OH:H2O2:H2O(1:1:5)•

Strip

PhotoresistLocal

TiNInterconnectThermalTreatinAr减小电阻

•1min@800°C28用TiN作为局部互连引线第二十八页，共三十八页。•Conformal

layerofSiO2

is

deposited

byCVDorLPCVD(typically1

µm)•PSG(磷硅玻璃)

or

BPSG(硼磷硅玻璃)•磷：Surface

passivation(表面钝化)•硼：Glassreflow

forpartialplanarization(加热，令表面平整)•ChemicalMechanicalPolishing

(CMP化学机械抛光)•Planarize

thewafersurface平坦化

•Polish

with

highpHsilicaslurry(硅酸盐研磨浆料)Conformal

Coat

and

Planarize2.8多层金属互连的形成SiO229

表面不平坦带来很多问题,两种解决方法：第二十九页，共三十八页。•Photolithography•

Mask

#12

pattern

alignmentand

UV

exposure•

Rinse

awaynon-pattern

PR•

SiO2

plasmaetch

•Anisotropicetch•StripPhotoresistVias

to

1stMetal30•选择第一层金属布线需要与下层器件结构形成连接的接触孔位置•

接触孔形成第三十页，共三十八页。

ViaDeposition

–

Tungsten

Plugs(插头)•TiNorTi/TiN

barrierlayer粘结层/阻挡层，增强金属与SiO2的粘附性•

Sputtering

orCVD(few

tens

of

nm)•

CVD

Tungsten

(W)•ChemicalMechanicalPolishing

(CMP)•Planarize

the

wafersurface•

Polishwith

highpHsilica

slurry31第三十一页，共三十八页。•

Etch

Contact

Holes(接触孔的蚀刻)orLine

Trenches(沟道)

•

Fill

etchedregions(蚀刻区的填充)

•

Planarize(平坦化)

–

CMPprocess –Alsoremoves

materialthat

“overflowed

holesortrenches”DamasceneProcess大马士革镶嵌工艺32大马士革镶嵌工艺包括：第三十二页，共三十八页。

•

Strip

PhotoresistMetal

#1

Deposition第一层金属布线Photolithography•Mask#13patternalignmentandUVexposure•Rinseawaynon-patternPR•Anisotropicplasmaetch33SiO2Al光刻胶•SputteredAluminum•AlwithsmallamountsofSiandCu-Cureduceselectromigration避免电迁移现象带来的断路

-Si降低接触电阻第三十三页，共三十八页。

Multiple

MetalLayers•DepositsOxideLayer•CMP•PhotolithographyMask#14•EtchVias•Depositviamaterial•CMP•DepositNextMetalLayer•PhotolithographyMask#15•FinalpassivationlayerofSi3N4isdepositedbyPECVDandpatternedwithMask#16.防止Na+、K+污染和封装中的机械损伤•Finalannealandalloyinforminggas(10%H2inN2)

•30min@400-450°C•形成良好的欧姆接触，降低Si/SiO2界面的电荷34SiO2WTiNSi3N4或SiO2第三十四页，共三十八页。Intel

µprocessorchip52MBSRAM

chips