基于FPGA的四位加法器设计

基于FPGA的四位加法器设计4位加法器设计。取开发板上的4位按键作为4位被加数，取4位拨码开关作为4位被加数，其中8个led灯取5位作为输出结果，led0-led3作为相加的结果，led4作为进位（LED亮表示低电平0，LED灭表示高电平1，）数码管以十进制数显示被加数，加数和相加的结果。包括vhdl文件、和vwf文件。利用两组按键作为两个加数输入，用数码管做加数显示和结果显示，开发板上只有4个数码管，但加数都是两位的，所以只能做轮流显示，用“=”键做显示切换。程序如下：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entityadder_4isport( clk:instd_logic;--时钟输入，应该输入分频后的clk enter:instd_logic;--显示切换，可以理解位“=”键 clear:instd_logic;--清除键，预留接口可扩展 key_num1:instd_logic_vector(3downto0);--加数1 key_num2:instd_logic_vector(3downto0);--加数2 duan:outstd_logic_vector(6downto0);--输出结果 wei:outstd_logic_vector(3downto0); led5:outstd_logic_vector(4downto0)--led结果显示 );endentity;architecturefunofadder_4issignalnum1,num2:std_logic_vector(3downto0);--中间信号定义signaladd_num1:integerrange15downto0;signaladd_num2:integerrange15downto0;signaladd_sum:integerrange30downto0;signalten_data:integerrange9downto0;signaladd_num1ge,add_num1shi,add_num2ge,add_num2shi,sumge,sumshi:integerrange9downto0;signalwei_data:integerrange0to3;begin duan<="1000000"whenten_data=0else--显示部分，数码管共阳 "1111001"whenten_data=1else "0100100"whenten_data=2else "0110000"whenten_data=3else "0111001"whenten_data=4else "0010010"whenten_data=5else "0000010"whenten_data=6else "1111000"whenten_data=7else "0000000"whenten_data=8else "0010000"; process(clk,clear,enter,key_num1,key_num2,num1,num2,add_num1ge,add_num1shi,add_num2ge,add_num2shi,sumge,sumshi) begin ifclear='0'then add_num1<=0; add_num2<=0; add_sum<=0; else --ifkey_num1/="1111"orkey_num2/="1111"then num1<=notkey_num1; num2<=notkey_num2;--加数处理，二进制转十进制。 add_num1<=conv_integer(num1(0))*1+conv_integer(num1(1))*2+conv_integer(num1(2))*4+conv_integer(num1(3))*8;add_num1ge<=(add_num1rem10);--个位，十位分离 add_num1shi<=((add_num1-add_num1ge)/10); add_num2<=conv_integer(num2(0))*1+conv_integer(num2(1))*2+conv_integer(num2(2))*4+conv_integer(num2(3))*8; add_num2ge<=(add_num2rem10); add_num2shi<=((add_num2-add_num2ge)/10); add_sum<=add_num1+add_num2; sumge<=(add_sumrem10); sumshi<=((add_sum-sumge)/10); led5<=('0'&num1)+('0'&num2); --endif; endif; ifclk'eventandclk='1'then wei_data<=wei_data+1; endif; ifenter='1'then casewei_datais when0=>ten_data<=add_num1ge;wei<="0001"; when1=>ten_data<=add_num1shi;wei<="0010"; when2=>ten_data<=add_num2ge;wei<="0100"; whenothers=>ten_data<=add_num2shi;wei<="1000"; endcase; else casewei_datais when0=>ten_data<=sumge;wei<="0001"; when1=>ten_data<=sumshi;wei<="0010"; when2=>ten_data<=0;wei<="0100"; whenothers=>ten_data<=0;wei<="1000"; endcase; endif; endprocess;endarchitecture;此程序为，在调试两周之后的没有问题的，学习班用的CYCLONE_IV_E:以下为50MHZ分频程序：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entitydefrequanceisport( in_5khz:instd_logic; out_1hz:outstd_logic );endentitydefrequance;architecturefunofdefrequanceissignalnum:integerrange0to50000;beginprocess(in_5khz,num)beginifin_5khz'eventandin_5khz='1'then num<=num+1; ifnum<25000then-- num<=0; out_1hz<='1'; elsifnum>25000andnum<50000then out_1hz<='0'; endif;endif;endpr