差分时钟拓扑分析

差分时钟拓扑分析PegasusYU一、 仿真条件采用差分时钟缓冲驱动器SY100EP14作为驱动器和接收器。将IBIS模型转为Cadence仿真的DML模型，进行差分信号完整性的仿真(LVPEC)。模型采用3.3V供电的模型。仿真75MHz差分时钟信号，环境为Typicalo二、 仿真过程a)PMC推荐拓扑Onm1LJB?OhmRECEIVER1R]STATE100EPH3VPECLInlO^EPMJVPECLobiIOOEPH3VPLCLIflDRIVERPULSES'dWipMJOSEPHJVPECLouiSialDOnm1LJB?OhmRECEIVER1R]STATE100EPH3VPECLInlO^EPMJVPECLobiIOOEPH3VPLCLIflDRIVERPULSES'dWipMJOSEPHJVPECLouiSialDDriverEeceiverCycletlitchTol[as]FTSModetlitchMonotonicHoiseXarein[-T]OvershootHich.[-T]OvershootL[■T]1DESItH.DRIVER.1DESICH.RECEIVER.13200.01056TypPASSFAIL-485.172583.29737.4731DESIGN.DRIVER.2DESIGH.RECEIVER.14200.01056TypPASSPASSNANAHADESIGN.DRIVER.1DESIGNRECEIVER.13_DESICN.RECEIVER.14_diff200.0105BTypFAILFAIL-432.5492385.67-997.66BJDODD300DESIGNRECEIVER13_DESIGNRECEIVER14_diffb)USI推荐拓扑DESIGNRECEIVER13_DE.SIGNRECE.IWR14_diffc)EMC推荐拓扑 DESIGNRECEIWR13_DE.SIGNRECEIVER.14_diff三、分析及改进很显然，上面的三种波形，都不满足时钟信号单调性的要求。EMC的设计，由于不正确的偏置，导致输入电压摆幅过大°USI的设计，没有加电源和地之间的电容，对电源平面受到的干扰考虑不足。将PMC的设计中，串接AC电容的容值改为1uf，见下图仿真波形，没有波形的优良改善。单调性仍然不过

r caseU-MonJm2111」二:心:41NLll」苫j iiiiIiiiiIiiiiIiir DESIGNRECEIVER13DESIGNRECEIVER14cliff上面PMC推荐的拓扑，是据同事所说，PMC有这样串接AC电容的连接方式。根据打印出来的PMC差分时钟设计部分原理图，从晶振到时钟驱动芯片，没有串接AC电容。从晶振的datasheet上看，也没有推荐使用AC串接电容。所以，下面采用不串接AC耦合电容的拓扑。JODOO1LW；ibIDDriverDESIGN.DRIVER.1HESIGIT.DRIVER.2HESIGIT.RECEIVER.13DESIGN.RECEIVER.14tlitchTol[心]0.010560.01056FTSModetlitchPASSPASSMonoton!cFAILFAIL-709.46-709.49Otersh.001Hieh.3059.233059.23Otersh.001Low[■刁1211.071209.66PropDelay[ns]DESIGN.DRIVER.1HESIGIT.RECEIVER.1J®I的EP14JODOO1LW；ibIDDriverDESIGN.DRIVER.1HESIGIT.DRIVER.2HESIGIT.RECEIVER.13DESIGN.RECEIVER.14tlitchTol[心]0.010560.01056FTSModetlitchPASSPASSMonoton!cFAILFAIL-709.46-709.49Otersh.001Hieh.3059.233059.23Otersh.001Low[■刁1211.071209.66PropDelay[ns]DESIGN.DRIVER.1HESIGIT.RECEIVER.1J®I的EP14胛PLCLinRECEIVERTEME.ii：「1DCkpMJ0DLPJ4_jy_PELlinjj:_DE20Q.Q1056|TfdFASSFASS 3T6 1695.38DRIVERPULSEij-JOOrpMIDuLPHJVPLCLuulK1DOLPHJVPLCLnul■-RM:-BfhDhm-F?5-RL5OhmDLJHICHK1RIPmoOhnDL2p^mtipipJODOhm>P3：-J-JDOhm DEWIGERECEIVER13_DESIGNRECE.IWR14_diff很显然，去除AC耦合电容后，波形得到改善，接收到的时钟信号已满足单调性要求。因此，应采用PMC推荐设计（不串接AC耦合电容）。可以看到，上面的波形仍然存在塌陷，属于不良的波形，仍然有可能影响单调性。因此，需要继续进行改进。之前的偏置上下拉部分，是放在靠近驱动器的一端。根据经验，放在接收器一边将会更好的吸收反射。改进的拓扑：JQQDQ[■IDDESIGN.DRIVER.1HESIGN.DRIVER.2DESIGN.DRIVER.1DESIGN.RECEIVER.13DESItlT.FLECEIVER.14DESIGN.RECEIVER.13tlitchTol0.010560.010560.01056FTSXodetlitchPASSFAILPASSMonoton!cFAILFAILPASSHoiseMarein顷]-868.15692.663OTershootHieh2471.991136.02OvershootLow顷]1237.821237.77-1134.92PropDelayg]1.51.51.5SwitchBelay-1.68664-1.689891.88488DRIVERPUL$EE.yJGDEpMItiOLPHJVJ'ECLriulDL1MJMfiiPJPJ00anrviDL3MIDVH-IPIPJQDOnfTiDL2UI-TFObiPIPJODDEJQQDQ[■IDDESIGN.DRIVER.1HESIGN.DRIVER.2DESIGN.DRIVER.1DESIGN.RECEIVER.13DESItlT.FLECEIVER.14DESIGN.RECEIVER.13tlitchTol0.010560.010560.01056FTSXodetlitchPASSFAILPASSMonoton!cFAILFAILPASSHoiseMarein顷]-868.15692.663OTershootHieh2471.991136.02OvershootLow顷]1237.821237.77-1134.92PropDelayg]1.51.51.5SwitchBelay-1.68664-1.689891.88488DRIVERPUL$EE.yJGDEpMItiOLPHJVJ'ECLriulDL1MJMfiiPJPJ00anrviDL3MIDVH-IPIPJQDOnfTiDL2UI-TFObiPIPJODDEJO&LPJJIVPECLinItlOLPIW'ECLriulRECEIVERTRJSltUE：r1b知14—J*IUOEPltJV_F-LCLincaseU-MemJan2111:1!?:2U20080 100 200 300Tiiiie[ns]DESIGNRECEIW.R13_DESIGNRECEIW.R14_diff很明显，波形已得到很好的改善。对于时钟信号边沿的单调性要求，已达到要求。并且电平部分的过冲也得到控制。四、结论1）采用下图的拓扑方式连接差分时钟信号（即PMC的推荐）ClIcoonpF10OLPI<^_PECLnu1IDOEPUJVLCLinJOODOpF&?.&OhmDL1pjmfiipjpJ00OhmDL3Hirra-ipipJODOhmDL2HI-UObiPIFJODOhmDRIVERPULSEE.yJ'3DEpMItluLPN山,PECLod旺CE1VERTRjmTES—OOepMJOC-EPJJIVPECLinD]R]收器tchBelay0 100 200 300Tiiiie[ns]DESIGNRECEIW.R13_DESIGNRECEIW.R14_diff很明显，波形已得到很好的改善。对于时钟信号边沿的单调性要求，已达到要求。并且电平部分的过冲也得到控制。四、结论1）采用下图的拓扑方式连接差分时钟信号（即PMC的推荐）ClIcoonpF10OLPI<^_PECLnu1IDOEPUJVLCLinJOODOpF&?.&OhmDL1pjmfiipjpJ00OhmDL3Hirra-ipipJODOhmDL2HI-UObiPIFJODOhmDRIVERPULSEE.yJ'3DEpMItluLPN山,PECLod旺CE1VERTRjmTES—OOepMJOC-EPJJIVPECLinD]R]收器tchBelay[ns]0.0105BITzdFAILFAIL-868.15NA1237.771.5-1.68989ir/M，欧％51136.02-1134.321.51.884882471.99-1.686640.01056TypPASSFAIL1237.821.5五、进一步验证Fast和Slow是两种极限仿真条件。如果在这两种条件下，时钟能够满足信号完整性要求，那么实际的信号就不会出问题。即便不能满足Fast和Slow条件，只要typical条件下足够好，实际情况下，出问题的概论会很小。SialDDriverEeceiverCtcIetlitchTol[ns]FTSModetlitchMonotonicHoiseMar[-T]1DESIGN.DRIVER.2DESIGN.RECEIVER.145一0.007771SlowPASSPASSNA2__1DESIGN.DRIVER.1DESIGN.RECEIVER.13_DESI&1T.RECEIVER.[50.007771SlowPASSPASS33.5343DESIGN.DRIVER.1DESIGN.FlECEIVER.1350.012224FastPASSFAIL31.1431.12DESIGN.DRIVER.2DESIGN.RECEIVER.1450.012224FastPASSFAIL土 1DESIGN.DRIVER.1DESIGN.RECEIVER.13_DESIC1T.RECEIVER.14_diff[50.012224FastPASSPASS123.7393DESIGN.DRIVER.1DESIGN.RECEIVER.1350.01056TfpPASSFAIL-65.39-S6S.