CPLD实验 数字时钟 波形发生器 简单组合逻辑设计

CPLD实验

一实验要求：熟练运用MAX+PLUSII分析组合逻辑电路、时序电路，能够运用VHDL对简单的逻辑电路功能进行描述。二、实验结果要求对仿真结果生成的仿真波形文件进行保存，并对结果进行分析说明。

实验1：简单组合逻辑设计

实验2：数码管扫描电路

libraryIEEE;useIEEE.std_logic_1164.all;entityxdeledisport(d_in:inSTD_LOGIC_VECTOR(3downto0);a:outSTD_LOGIC;b:outSTD_LOGIC;c:outSTD_LOGIC;d:outSTD_LOGIC;e:outSTD_LOGIC;f:outSTD_LOGIC;g:outSTD_LOGIC);endxdeled;begin--<<enteryourstatementshere>>process(d_in)typedata_outisarray(0to6)ofstd_logic;variableoutp:data_out;begincased_iniswhen"0000"=>outp:="1111110";when"0001"=>outp:="0110000";when"0010"=>outp:="1101101";when"0011"=>outp:="1111001";when"0100"=>outp:="0110011";when"0101"=>outp:="1011011";when"0110"=>outp:="1011111";

when"0111"=>outp:="1110000";when"1000"=>outp:="1111111";when"1001"=>outp:="1111011";when"1010"=>outp:="1110111";when"1011"=>outp:="0011111";when"1100"=>outp:="1001110";when"1101"=>outp:="0111101";when"1110"=>outp:="1001111";when"1111"=>outp:="1000111";whenothers=>null;endcase;a<=outp(0);b<=outp(1);c<=outp(2);d<=outp(3);e<=outp(4);f<=outp(5);g<=outp(6);endprocess;endxdeled;实验3：计数器电路设计（8位二进制同步计数器）实验4：波形发生器

1、正斜率斜波2、负斜率斜波3、锯齿波4、递增阶梯波

libraryIEEE;useIEEE.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;

entitywavegeneratorisport(

clk:inSTD_LOGIC;reset:inSTD_LOGIC;mode:inSTD_LOGIC_VECTOR(1downto0);d_out:outSTD_LOGIC_VECTOR(7downto0));endwavegenerator;architecturewavegenerator_archofwavegeneratorissignalda:std_logic_vector(7downto0);begin--<<enteryourstatementshere>>

process(clk,reset,mode,da)variableporn:std_logic;beginifreset='0'then

da<="00000000";d_out<="00000000";porn:='0';elseifclk='1'andclk'eventthencasemodeiswhen"00"=>ifda<255then

da<=da+1;else

da<="00000000";endif;

when"01"=>ifda=0then

da<="11111111";else

da<=da-1;endif;when"10"=>ifporn='0'thenifda<255then

da<=da+1;elseporn:='1';endif;elseifda>0then

da<=da-1;elseporn:='0';endif;endif;when"11"=>ifda<240then

da<=da+32;else

da<="00000000";endif;whenothers=>

da<="00000000";endcase;endif;d_out<=da;endif;endprocess;

endwavegenerator_arch;实验5：全功能计数器VHDL描述

--MAX+plusIIVHDLExample--EfficientCounterInference--Copyright(c)1994AlteraCorporation--downloadfrom:&

LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;

ENTITYcountersIS

PORT ( d :IN INTEGERRANGE0TO255;

clk :IN BIT; clear :IN BIT; ld :IN BIT; enable :IN BIT; up_down :IN BIT;

qa :OUT INTEGERRANGE0TO255;

qb :OUT INTEGERRANGE0TO255; qc :OUT INTEGERRANGE0TO255;

qd:OUT INTEGERRANGE0TO255;

qe :OUT INTEGERRANGE0TO255;

qf :OUT INTEGERRANGE0TO255;

qg :OUT INTEGERRANGE0TO255;

qh :OUT INTEGERRANGE0TO255;

qi :OUT INTEGERRANGE0TO255;

qj :OUT INTEGERRANGE0TO255;

qk :OUT INTEGERRANGE0TO255;

ql :OUT INTEGERRANGE0TO255;

qm :OUT INTEGERRANGE0TO255;

qn :OUT INTEGERRANGE0TO255 );ENDcounters;

ARCHITECTUREaOFcountersISBEGIN --Anenablecounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFenable='1'THEN

cnt:=cnt+1; ENDIF; ENDIF;

qa <=cnt;

ENDPROCESS;--Asynchronousloadcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFld='0'THEN

cnt:=d; ELSE

cnt:=cnt+1; ENDIF; ENDIF;

qb <= cnt; ENDPROCESS;--Asynchronousclearcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFclear='0'THEN

cnt:=0; ELSE

cnt:=cnt+1; ENDIF; ENDIF;

qc <= cnt;

ENDPROCESS;

--Anup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN

cnt:=cnt+direction; ENDIF;

qd <= cnt;

ENDPROCESS;--Asynchronousloadenablecounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFld='0'THEN

cnt:=d; ELSE IFenable='1'THEN

cnt:=cnt+1; ENDIF; ENDIF; ENDIF;

qe <= cnt;

ENDPROCESS;--Anenableup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN IFenable='1'THEN

cnt:=cnt+direction; ENDIF; ENDIF;

qf <= cnt;

ENDPROCESS;

--Asynchronousclearenablecounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFclear='0'THEN

cnt:=0; ELSE IFenable='1'THEN

cnt:=cnt+1; ENDIF; ENDIF; ENDIF;

qg <= cnt;

ENDPROCESS;--Asynchronousloadclearcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFclear='0'THEN

cnt:=0; ELSE IFld='0'THEN

cnt:=d; ELSE

cnt:=cnt+1; ENDIF; ENDIF; ENDIF;

qh <= cnt;

ENDPROCESS;

--Asynchronousloadup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN

IFld='0'THEN

cnt:=d; ELSE

cnt:=cnt+direction; ENDIF; ENDIF;

qi <= cnt;

ENDPROCESS;

--Asynchronousloadenableup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN IFld='0'THEN

cnt:=d; ELSE IFenable='1'THEN

cnt:=cnt+direction; ENDIF; ENDIF; ENDIF;

qj <= cnt;

ENDPROCESS;--Asynchronousclearloadenablecounter PROCESS(clk) VARIABLE cnt:INTEGERRANGE0TO255; BEGIN IF(clk'EVENTANDclk='1')THEN IFclear='0'THEN

cnt:=0; ELSE IFld='0'THEN

cnt:=d; ELSE IFenable='1'THEN

cnt:=cnt+1; ENDIF; ENDIF; ENDIF; ENDIF;

qk <= cnt;

ENDPROCESS;

--Asynchronousclearup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN

IFclear='0'THEN

cnt:=0; ELSE

cnt:=cnt+direction; ENDIF; ENDIF;

ql <= cnt;

ENDPROCESS;--Asynchronousclearenableup/downcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; VARIABLE direction :INTEGER; BEGIN IF(up_down='1')THEN direction:=1; ELSE direction:=-1; ENDIF;

IF(clk'EVENTANDclk='1')THEN IFclear='0'THEN

cnt:=0; ELSE IFenable='1'THEN

cnt:=cnt+direction; ENDIF; ENDIF; ENDIF;

qm <= cnt;

ENDPROCESS;--Amodulus200upcounter PROCESS(clk) VARIABLE cnt :INTEGERRANGE0TO255; CONSTANT modulus :INTEGER:=200; BEGIN IF(clk'EVENTANDclk='1')THEN IFcnt=modulusTHEN

cnt:=0; ELSE

cnt:=cnt+1; ENDIF; ENDIF;

qn <= cnt;

ENDPROCESS;ENDa;实验6：地址译码器VHDL描述

--M68008AddressDecoder--Addressdecoderforthem68008--asbarmustbe'0'toenableanyoutput--csbar(0):X"00000"toX"01FFF"--csbar(1):X"40000"toX"43FFF"--csbar(2):X"08000"toX"0AFFF"--csbar(3):X"E0000"toX"E01FF"--downloadfrom&

libraryieee;useieee.std_logic_1164.all;entityaddrdecisport(

asbar:instd_logic;address:instd_logic_vector(19downto0);

csbar:outstd_logic_vector(3downto0));endentityaddrde