第12章 系统仿真

EDA技术实用教程第12章系统仿真12.1仿真

仿真也称模拟（Simulation）是对电路设计的一种间接的检测方法，是利用计算机对整个硬件系统进行模拟检测，但却可以不接触具体的硬件系统。

12.2VHDL源程序仿真

图12-1VHDL仿真流程

12.2VHDL源程序仿真

【例12-1】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand1ISPORT(aaa,bbb:INSTD_LOGIC;ccc:OUTSTD_LOGIC);ENDand1;ARCHITECTUREoneOFand1ISBEGINccc<=aaaANDbbb;END;

12.2VHDL源程序仿真

【例12-2】LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYTRIBUF_and1ISGENERIC(ttri:TIME:=1ns;ttxz:TIME:=1ns;ttzx:TIME:=1ns);PORT(in1:INstd_logic;oe:INstd_logic;y:OUTstd_logic);ENDTRIBUF_and1;ARCHITECTUREbehaviorOFTRIBUF_and1ISBEGINPROCESS(in1,oe)BEGINIFoe‘EVENTTHEN（接下页）IFoe='0'THENy<=TRANSPORT'Z'AFTERttxz;ELSIFoe='1'THENy<=TRANSPORTin1AFTERttzx;ENDIF;ELSIFoe='1'THENy<=TRANSPORTin1AFTERttri;ELSIFoe='0'THENy<=TRANSPORT'Z'AFTERttxz;ENDIF;ENDPROCESS;ENDbehavior;LIBRARYIEEE;USEIEEE.std_logic_1164.all;USEwork.tribuf_and1;ENTITYand1ISPORT(aaa:INstd_logic;bbb:INstd_logic;ccc:OUTstd_logic);ENDand1;ARCHITECTUREEPF10K10LC84_a3OFand1IS......ENDEPF10K10LC84_a3;

12.3仿真激励信号的产生

【例12-3】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYADDER4ISPORT(a,b:ININTEGERRANGE0TO15;c:OUTINTEGERRANGE0TO15);ENDADDER4;ARCHITECTUREoneOFADDER4ISBEGINc<=a+b;ENDone;

第一种方法：12.3仿真激励信号的产生

【例12-4】ENTITYSIGGENISPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);END;ARCHITECTURESimOFSIGGENISBEGINsig1<=10,5AFTER200ns,8AFTER400ns;sig2<=3,4AFTER100ns,6AFTER300ns;END;

12.3仿真激励信号的产生

图12-2SIGGEN的仿真输出波形

12.3仿真激励信号的产生

【例12-5】ENTITYBENCHISEND;ARCHITECTUREoneOFBENCHISCOMPONENTADDER4PORT(a,b:integerrange0to15;c:OUTINTEGERRANGE0TO15);ENDCOMPONENT;COMPONENTSIGGENPORT(sig1:OUTINTEGERRANGE0TO15;sig2:OUTINTEGERRANGE0TO15);ENDCOMPONENT;SIGNALa,b,c:INTEGERRANGE0TO15;BEGINU1:ADDER4PORTMAP(a,b,c);U2:SIGGENPORTMAP(sig1=>a,sig2=>b);END;

12.3仿真激励信号的产生

图12-3BENCH仿真波形图

12.3仿真激励信号的产生

force<信号名><值>[<时间>][,<值><时间>…][-repeat<周期>]

第二种方法：forcea0 （强制信号的当前值为0）forceb00,110（强制信号b在时刻0的值为0，在时刻10的值为1）forceclk00,115–repeat20 （clk为周期信号，周期为20

forcea100,5200,8400forceb30,4100,6300

12.4VHDL测试基准

【例12-6】LibraryIEEE;useIEEE.std_logic_1164.all;entitycounter8isport(CLK，CE，LOAD，DIR，RESET:inSTD_LOGIC;DIN:inINTEGERrange0to255;COUNT:outINTEGERrange0to255);endcounter8;architecturecounter8_archofcounter8isbeginprocess(CLK,RESET)variableCOUNTER:INTEGERrange0to255;beginifRESET='1'thenCOUNTER:=0;elsifCLK='1'andCLK'eventthenifLOAD='1'thenCOUNTER:=DIN;（接下页）ElseifCE='1'thenifDIR='1'thenifCOUNTER=255thenCOUNTER:=0;ElseCOUNTER:=COUNTER+1;endif;elseifCOUNTER=0thenCOUNTER:=255;ElseCOUNTER:=COUNTER-1;endif;endif;endif;endif;endif;COUNT<=COUNTER;endprocess;endcounter8_arch;

12.4VHDL测试基准

【例12-7】Entitytestbenchisendtestbench;Architecturetestbench_archoftestbenchisFileRESULTS:TEXTopenWRITE_MODEis"results.txt";Componentcounter8port(CLK:inSTD_LOGIC; RESET:inSTD_LOGIC; CE,LOAD,DIR:inSTD_LOGIC; DIN:inINTEGERrange0to255; COUNT:outINTEGERrange0to255);endcomponent;sharedvariableend_sim:BOOLEAN:=false;signalCLK,RESET,CE,LOAD,DIR:STD_LOGIC;signalDIN:INTEGERrange0to255;signalCOUNT:INTEGERrange0to255;procedureWRITE_RESULTS ( CLK，CE，LOAD，LOAD，RESET:STD_LOGIC;（接下页）DIN，COUNT:INTEGER)isVariableV_OUT:LINE;Begin write(V_OUT,now,right,16,ps);--输入时间 write(V_OUT,CLK,right,2); write(V_OUT,RESET,right,2); write(V_OUT,CE,right,2); write(V_OUT,LOAD,right,2); write(V_OUT,DIR,right,2); write(V_OUT,DIN,right,257); --writeoutputs write(V_OUT,COUNT,right,257); writeline(RESULTS,V_OUT);endWRITE_RESULTS;begin UUT:COUNTER8 portmap(CLK=>CLK,RESET=>RESET, CE=>CE,LOAD=>LOAD, DIR=>DIR, DIN=>DIN, COUNT=>COUNT);CLK_IN: process Begin（接下页）

ifend_sim=falsethenCLK<='0'; Waitfor15ns; CLk<='1'; Waitfor15ns; Else Wait; endif; endprocess;STIMULUS:process Begin RESET <='1'; CE <='1'; --计数使能

DIR <='1'; --加法计数

DIN <=250; --输入数据 LOAD <='0'; --禁止加载输入的数据waitfor15ns;RESET <='0';waitfor1us;CE <='0'; --禁止计数脉冲信号进入

waitfor200ns;CE <='1';waitfor200ns;（接下页）

DIR <='0';waitfor500ns;LOAD <='1';waitfor60ns;LOAD <='0'; waitfor500ns;DIN <=60;DIR <='1';LOAD <='1';waitfor60ns;LOAD <='0';waitfor1us; CE <='0';waitfor500ns;CE <='1';waitfor500ns;end_sim:=true; wait;endprocess; WRITE_TO_FILE:WRITE_RESULTS(CLK,RESET,CE,LOAD,DIR,DIN,COUNT);Endtestbench_arch;12.4VHDL测试基准

图12-48位计数器测试基准仿真部分波形图

12.5VHDL系统级仿真

图12-5VHDL系统仿真模型示意图

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

12.5VHDL系统级仿真

【例12-8】LIBRARYieee;USEieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITYcnt4IS PORT ( rst:INSTD_LOGIC; d:INSTD_LOGIC_VECTOR(3downto0); load:INSTD_LOGIC; clk,ce:INSTD_LOGIC; q:OUTSTD_LOGIC_VECTOR(3downto0); cout:OUTSTD_LOGIC );ENDcnt4;ARCHITECTUREsynOFcnt4IS signalcount:std_logic_vector(3downto0);BEGIN（接下页）12.5VHDL系统级仿真

cntproc:process(clk,rst)begin ifrst='1'then count<=(others=>'0'); elsifrising_edge(clk)then ifce='1'then ifload='1'then count<=d; else count<=count+1; endif; endif; endif;endprocess;coutproc:process(clk,rst)begin ifrst='1'then cout<='0'; elsifrising_edge(clk)then ifcount="1111"then cout<='1'; else cout<='0'; endif; endif;endprocess;q<=count;ENDsyn;12.6使用ModelSim进行仿真

图12-6ModelSim的启动界面

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

图12-7建立工程建立项目

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

图12-8开始编译仿真文件

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

图12-9ModelSim编译时的提示信息

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

图12-10装载设计模块

12.5VHDL系统级仿真

图12-11ModelSim的仿真观察窗

12.5VHDL系统级仿真

12.5VHDL系统级仿真

【例12-9】libraryieee;useieee.std_logic_1164.all;ENTITYwavegenIS PORT ( clk,rst:OUTSTD_LOGIC );endwavegen;ARCHITECTUREsimOFwavegenis constantcycle:Time:=10ns;BEGIN processbegin clk<='0'; waitforcycle/2; clk<='1'; waitforcycle/2; endprocess; processbegin rst<='1'; waitforcycle*5; rst<='0'; wait; endprocess;ENDsim;12.6使用ModelSim进行仿真

图12-12ModelSim的波形观察窗

12.5VHDL系统级仿真

12.6使用ModelSim进行仿真

图12-12时钟与复位信号生成

12.5VHDL系统级仿真

12.7VHDL的RTL表述

12.5VHDL系统级仿真

12.7.1行为描述

【例12-10】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL；ENTITYcunter_upISPORT(reset,clock:INSTD_LOGIC;counter:OUTSTD_LOGIC_VECTO