华南理工大学2021年数字系统设计(全英)B卷

4/4华南理工大学2021年数字系统设计(全英)B卷1.Multiplechoicetest（2ⅹ5=10marks）

1.WhichofthefollowingstatementsonVHDLprocessisnottrue（C）

A．asignalcanbereadinmultipleprocesses;

B.asignalcanbeassignedvaluesformultipletimesinaprocess,however,onlythelast

assignmenttakeseffect;

C．asignalcanbeassignedvaluesindifferentprocess;

D．aprocesscanbetriggeredeitherbymeansofsensitivitylistorbywaitstatement;

2.Whichofthefollowingstatementsisnottrue（D）

A.Theworkingfrequencyofasynchronousdigitalsystemshouldn’texceedthereciprocal(倒数)

ofitsmaximaldelay;

B.Theworkingfrequencyofasynchronousdigitalsystemislimitedbythedelayofits

components.

C.Asynchronousdigitalsystemismoreefficientintermsofresourcesthansynchronoussystem.

D.Asynchronousdigitalsystemismorereliablethansynchronoussystem.

3.Whichofthefollowingstatementsonsynthesisisnottrue（D）

A.Synthesisisatransformationprocessfromonerepresentationofthedesigntoanother

representationform；

B.SynthesistransformsthehighlevelHDLtolowlevelhardwarenetlist,whichisproduced

accordingtoFPGA/CPLDstructure；

C.Synthesisisusuallylimitedbythesurfaceandspeedofthecircuit；

D.Synthesisisamappingprocessfromhighleveldescriptiontolowlevelhardware

representation.Themappingrelationshipisuniqueandthesynthesisresultisunique.

4.WhichofthefollowingstatementsonVHDLsimulation

B.Apulsesignalcan’tpropagatethroughthepathifitsdurationislessthantransportdelay;

C.ForaVHDLsignal,itsinitialvalueassignedinitsdeclarationpartisvalidinsimulationonly;it’signoredbytheVHDLsynthesis;

D.Simulationisactuallyaprocessofcheckingandverification;

5.Instatemachinecoding,（A）cansavetheresourcesfordecodingandreducetheriskofillegalstatesatthepriceofmoreregisterresources:

A.one-hotcodingB.randomcodingC.naturalbinarycodingD.graycode

2.ShortQ&A（10ⅹ2=20marks）

1、Thefollowingfigureshowsthecriticalpathofadigitalsystem.(10marks)

(1)Pleasegiveabriefexplanationrespectivelyforthetimingparametersincludingtsu,thold,

tc-q,tlogic

(2)Accordingthetimingparametersinthefigure,calculatethemaximaldelayτmaxofthe

criticalpath(orthemaximalworkingfrequencyfmaxofthesystem).

Setuptime：

Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimebeforetheclockedge(registersetuptimeortSU).ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed

Holdtime：

Toensurereliableoperation,theinputtoaregistermustbestableforaminimumtimeaftertheclockedge(registerholdtimeortH).ifthetimeisnotlongenough,reliableoperationcannotbeguaranteed.

Tcq

Theregisteroutputthenisavailableafteraspecifiedclock-to-outputdelay(tcoortcq).

tlogic

Theworstcombinationalogicdealy

τmax=tcq+tsu+tlogic

2.PleasedrawtheRTLdiagramsforthefollowing2piecesVHDLcodes（10marks）

（1）

process(op,x,y)

begin

ifop=‘0’then

resultDoutDoutDoutNull;

endcase;

endprocess;

endarchitecture;

2、UsingVHDL,describethe2stimulishownbythefollowingdiagram,asaparttestbench。(6marks)

…

SignalS1：std_logic;

SignalS2：std_logic;

…

Process

Begin

S1YYYNull;

endcase;

endprocess;

endarchitecture;

4、readthefollowingVHDLcodes,andexplainitsfunction（6marks）

Libraryieee;

Useieee.std_logic_1164.all;

entitys4is

port(clk,rst:instd_logic;

load,en:instd_logic;

din:inSTD_LOGIC_VECTOR(7downto0);

qb:outstd_logic);

ends4;

architecturebehavofs4is

signalreg8:std_logic_vector(7downto0);

begin

process(clk,RST,load,en)

begin

ifrst='1'then

reg8'0');

elsifCLK'EVENTANDCLK='1'then

ifload='1'then

reg8x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

WHENs2=>x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

WHENs3=>x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

WHENs4=>x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

WHENs5=>x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

WHENs6=>x(6downto0):=x(7downto1);x(7):=data;cnt:="0000";

W