数字电路软件实验-8学时fpga新

§3.3

VHDL的设计实例8位反相器的结构描述ENTITY

inv_8_bit

ISPORT

(x:

IN

STD_LOGIC_VECTOR(1TO

8);y:

OUT

STD_LOGIC_VECTOR(1TO

8);END

inv_8_bit;ARCHITECTURE

struct

OF

inv_8_bit

ISCOMPONENT

invPORT

(i:

IN

STD_LOGIC;o:

OUT

STD_LOGIC);END

COMPONENT;BEGINu:

FOR

n

IN 1

TO

8

GENERATE;v:

inv

FORT

MAP

(x(n),y(n));END

GENERATE;END

struct;元件语句：又称元件例化就是引入一种连接关系，可以把以前设计好的设计实体定义为一个元件，然后将此元件与当前的设计实体的指定端口相连接，从而为当前的设计实体引入一个新的低一级的设计层次。元件定义语句的格式：COMPONENT

元件名

ISPORT（信号名表）；END

COMPONENT;元件调用语句的格式：例化名：元件名

PORTMAP（信号名表）；生成语句：生成语句用来产生多个相同的结构，生成语句有一种作用，可

一组完全相同的元件或电路结构。FOR

循环变量

IN

取值范围

GENERATE并发处理语句；END

GENERATE[标号]；用半加器和“或门”构成全加器。half_adder1half_adder2a

bcinc1

s1scoutc2U2U1half_adderabscLIBRARY

IEEE；USE

IEEE

std_logic_1164.ALL;ENTITY

full_adder

ISPORT

(a，b，cin:

IN

BIT;s,

cout: OUT

BIT);END

full_adder;ARCHITECTURE

arc

OF

full_adder

ISCOMPONENT

half_adderPORT(a,

b:

IN

BIT;s,

c:

OUT

BIT);END

COMPONENT;SIGNAL s1,

c1,

c2:

BIT;BEGINU1:

half_adder

PORT

MAP(a,b,s1,c1);U2:

half_adder

PORT

MAP(s1,cin,s,c2);cout<=

c1

OR

c2;END

arc;三——八译

的数据流描述。LIBRARY

IEEE；USE

IEEE

std_logic_1163.ALL;ENTITY

decoder3_8

ISPORT

(g1，g2a，g2b:

IN

STD_LOGIC;a，b，c：IN

STD_LOGIC;y:

OUT

STD_LOGIC_VECTOR(7DOWNTO

0);END

decoder3_8;ARCHITECTURE

rtl

OF

decoder3_8

ISSIGNAL

comb:

STD_LOGIC_VECTOR(2DOWNTO

0);BEGINcomb

<=

c

&

b

&

a

;PROCESS

(g1，g2a，g2b，comb）BEGINIF(g1=‘1’

AND

g2a=‘0’

AND

g2b=‘0’)

THENCASE

comb

ISWHEN“000”=>y<=“11111110”;WHEN“001”=>y<=“11111101”;WHEN“010”=>y<=“11111011”;WHEN“011”=>y<=“11110111”;WHEN“100”=>y<=“11101111”;WHEN“101”=>y<=“11011111”;WHEN“110”=>y<=“10111111”;WHEN“111”=>y<=“01111111”;WHEN OTHERS

=>y<=“xxxxxxxx”;END

CASE；END

IF；END

PROCESS；END

rtl；三态输出“与非”门的性能描述。ENTITY

stm

ISPORT

(i1,

i2,

en:

IN

STD_LOGIC;y:

OUT

STD_LOGIC);END

stm;ARCHITECTURE

behave

OF

stm

ISBEGINPROCESS(i1,

i2,

en)BEGINIF en

=‘1’

THENy<

=

i1

NAND

i2;ELSEY

<=‘Z’;END

IF;END

PROCESS;END

behave;对上述三态门还可以用条件赋值语句来描述，就得到三态门的数据流描述：ARCHITECTURE

dflow

OF

stm

ISBEGINy<=

i1

NAND

i2

WHEN

(en=“1’)ELSEy

<=

‘Z’;END

dflow;钟控型触发器的描述，上升沿触发的D触发器。ENTITY

DF

ISPORT

(d,

clk:

IN

BIT;q,qb:

OUT

BIT);END

DF;ARCHITECTURE

behave

OF

DF

ISBEGINPROCESS(clk)BEGINIF(clk

‘

EVENT

AND

clk

=‘1’)

THENq<=

d;qb<=

NOT

d;END

IF;ENDPROCESS;END

behave;带有异步置位/复位功能上升沿触发的D触发器。LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;ENTITY

dff_2

ISPORT

(d,

clk, s,

r:

IN

STD_LOGIC;q,

qb:

OUT

STD_LOGIC);END

dff_2;ARCHITECTURE

beh

OF

dff_2

ISBEGINBEGINPROCESS(clk,

s,

r)BEGINIF

(s

=

‘0’

AND

r

=‘1’

)

THENq<=‘1

’;qb

<

=‘0’;ELSIF

(

s

=‘1’

AND

r

=‘0’

)

THENq<=‘0

’;qb

<

=‘1’;ELSIF

(

clk’

EVENT

AND clk

=‘1’

)

THENq

<=

d;qb

<=NOT

d;END

IF;END

PROCESS;END

beh;上述语句中就是异步置位/复位，低有效。设计同步复位上升沿触发的D触发器。其电路图如下。QCPdclkclr

1

DqLIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;ENTITY

dff_4

ISPORT

(d,

clk,

clr:

IN

STD_LOGIC;q:

OUT

STD_LOGIC);END

dff_4;ARCHITECTURE

rtl

OF

dff_4

ISBEGINBEGINPROCESS(clk)BEGINIF

(clk’

EVENT

AND clk

=‘1’

)

THENIF

(clr

=

‘1

’)

THENq

<=

‘0’;ELSEq

<=d;END

IF;ENDPROCESS;END

rtl;设计一个分频器，并通过修改程序中的参数来实现不同倍数的分频。LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

divider_n

ISGENERIC

(n:

INTEGER:=10);PORT

(clki

:

IN

STD_LOGIC;指令：generic

类属参数说明；格式：GENERIC（常数名字表：数据类型[：=设定值]类属参数说明是实体说明组织中的可选项，必须放在端口说明前，用于指定参数。VHDL中的对象：1、常量；2、变量；3、信号。Signal

信号可以代表电路是实体动态交换数据各元件之间的连接线，段。Signal

信号名：数据类型

约束条件：=

表达式VARIABLE

用于对可变数据的临时

，变量只能在进程语句、函数语句和过程语句结构中使用，它是一个局部量。VARIABLE

变量名：数据类型

约束条件：=

表达式clko:

OUT

STD_LOGIC);END

divider_n

；ARCHITECTURE

arc_divider_n

OFdivider_n

ISSIGNAL

qout:

STD_LOGIC;SIGNAL

counter:

INTEGER;BEGINclko<=qout;PROCESS(clki)BEGINIF

(clki’

EVENT

AND clki

=‘1’

)

THENIF

(counter

=

n-1

)

THENqout<=

NOT

qout;counter<=

0;ELSEcounter

<

=

counter

+1;END

IF;END

IF;END

PROCESS;END

arc_divider_n;设计一个十进制计数器，要求代允许计数端和清零端，计数允许端和清零端均为高有效，真值表如下。输入端输出端clrenclkqdqcqbqa1XX000000X不变不变不变不变01计数值加1enclrclkqdqcqbqa十进制计数器LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

count_10

ISPORT

(clk,

clr,

en

:

IN

STD_LOGIC;qa,

qb,

qc,

qd:

OUT

STD_LOGIC);END

count_10;ARCHITECTURE

arc_count10

OF

count_10ISSIGNAL

qout:

STD_LOGIC_VECTOR(3DOWNTO

0);BEGINqa<=qout(0);qb<=qout(1);qc<

=qout(2);qd<=qout(3);PROCESS(clk,

clr)BEGINIF

(clr=‘1’)

THENqout<=

“0000”;ELSIF(clk’

EVENT

AND

clk

=‘1’)

THENIF

(en

=

‘1’)

THENIF

(qout

=“1001”)

THENqout<

=“0000”;ELSEqout<=

qout

+

‘1’;ENDIF;END

IF;END

IF;ENDPROCESS;END

arc_count10;设计一个同步可逆计数器，要求代允许计数端和清零端，方向控制端，计数允许端和清零端均为高有效，真值表如下。输入端输出端clrupdownloadclkQ(3)Q(2)Q(1)Q(0)1XXX00000X1X预置输入端D状态010计数值加1000计数值减1真值表D(3)D(2)D(1)D(0)clrclkQ(3)Q(2)Q(1)Q(0)十进制计数器load

updownLIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

count_4

ISPORT

(clk,

clr,

load,

updown:

INSTD_LOGIC;d:

IN

STD_LOGIC_VECTOR

(3DOWNTO

0));q:

OUT

STD_LOGIC_VECTOR(3DOWNTO

0));END

count_4

；ARCHITECTURE

arc_count4

OF

count_4ISBEGINPROCESS(clk,

clr,

load)BEGINIF

(clr

=‘1’)

THENq

<=

“0000”;ELSIF(load

=

‘1’

)THENq<=dELSIF

(clk‘EVENT

AND

clk

=‘1’)

THENIF

(updown

=‘1’)

THENq

<=

q+1

;ELSEq

<=

q-1

;ENDIF;END

IF;END

PROCESS;END

arc_count4;设计一个moore型状态机。输出信号仅是现态的函数。S0/0S1/1S3/00101S2/01001外输入输出LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

Std_logic

_UNSIGNED.

ALL;ENTITY

moore

ISPORT

(CO,

DIN:

IN

STD_LOGIC;OP: OUT

STD_LOGIC);END

moore;ARCHITECTURE

behave

OF

moore

ISTYPE

STATE

IS (S0,

S1,

S2,

S3);SINGAL

Presentstate

:STATE;SINGAL

Nextstate

:

STATE;BEGINSwitchToNextstate:

Process

(CP)BEGINIF

(CP

‘EVENT

AND

CP

=‘1’)

THEN