dsp原理今日内容

C281x

Block

Diagram32x32

bitMultiplierSectoredFlashProgramBusDataBusRAMBootROM32-bitAuxiliaryRegisters332

bitTimersRealtimeJTAGRegister

BusCPUR-M-WAtomicALUPIEInterruptManagerEventManagerAEventManagerB12-bit

ADCWatchdogMcBSPCAN2.0BSCI-ASCI-BSPIGPIO7

-27

-3SPI

Data

FlowSPI

Shift

RegisterSPI

Shift

Registershiftshift7

-4SPI

Dharacter

Justification11001001XXXX110010017

-57

-6；；硬件连接7

-7；；；

；并行串行；；；7

-8SPIRXBUF.15-0SPIDAT.15-0LSPCLKbaudrateclockpolarityclockphaseSPI

Block

DiagramLSBMSBSPITXBUF.15-0TX

FIFO_0TX

FIFO_15RX

FIFO_0RX

FIFO_157

-9：1.2.3.4.；；；

；；；；；5.；；；，；7

-10AddressRegisterNameSPICCRSPICTLSPISTSSPIBRRSPI-A

configuration

control

registerSPI-Aoperation

controlregisterSPI-A

status

registerSPI-A

baud

rate

register0x0070400x0070410x0070420x0070440x007046SPIEMUSPI-A

emulation

buffer

register0x007047SPIRXBUFSPI-A

serial

receive

buffer

register0x007048SPITXBUFSPI-A

serial

transmit

buffer

register0x007049SPIDATSPI-A

serial

data

register0x00704A0x00704B0x00704CSPIFFTXSPIFFRXSPIFFCTSPI-AFIFO

transmit

registerSPI-A

FIFO

receive

registerSPI-AFIFO

control

register0x00704FSPIPRISPI-A

priority

control

registerSPI-ARegisters7

-11SPI-A

Configuration

Control

RegisterSPICCR

@

0x007040SPI

CHAR.3-0CLOCK

POLARITYSPI

SW

RESET7

-12SPI-A

Operation

ControlRegisterSPICTL

@

0x007041CLOCK

PHASEOVERRUN

INT

ENABLEMASTER/SLAVETALKSPI

INT

ENABLE7

-13SPI-A

Baud

Rate

RegisterSPIBRR

@

0x007044SPI

BIT

RATESPICLK

signal

=LSPCLK(SPIBRR

+

1)LSPCLK4, SPIBRR

=

3

to

127, SPIBRR

=

0,

1,

or27

-14SPI-A

Status

RegisterSPISTS

@

0x007042TX

BUF

FULLSPI

INT

FLAGRECEIVER

OVERRUN7

-15GPIO

DGPIOD0

/

T1CTRIP_PDPINTAGPIOD1

/

T2CTRIP

/

EVASOCGPIOD5

/

T3CTRIP_PDPINTBGPIOD6

/

T4CTRIP

/

EVBSOCGPIO

EGPIOE0/XINT1_XBIOGPIOE1/XINT2_ADCSOCGPIOE2/XNMI_XINT13123456_T1CMPT2

_T2CMPGPIO

A

GPIOA0

/GPIOA1

/GPIOA2

/GPIOA3

/GPIOA4

/GPIOA5

/GPIOA6

/

T1GPIOA7

/GPIOA8

/CAP1_QEP1GPIOA9/GPIOA10

/GPIOA11

/GPIOA12

/GPIOA13

/CAP2_QEP2CAP3_QEPI1TDIRATCLKINAC1TRIPC2TRIPC3TRIPGPIOA14

/GPIOA15

/GPIO

FGPIOF0

/GPIOF1

/GPIOF2

/GPIOF3

/GPIOF4

/GPIOF5

/GPIOF6

/GPIOF7

/GPIOF8

/GPIOF9GPIOF10

/GPIOF11

/GPIOF12

/GPIOF13

/SPISIMOASPISOMIASPICLKASPISTEASCITXDASCIRXDACANTXACANRXAMCLKXA/

MCLKRAMFSXAMFSRAMDXAMDRAGPIO

BGPIOB0/////789101112GPIOB1GPIOB2GPIOB3GPIOB4GPIOB5/////////////GPIOB6T3T4_T3CMPGPIOB7_T4CMPGPIOB8CAP4_QEP3CAP5_QEP4CAP6_QEPI2TDIRBTCLKINBC4TRIPC5TRIPC6TRIPSCITXDBSCIRXDBGPIOB9GPIOB10GPIOB11GPIOB12GPIOB13GPIOB14GPIOB15GPIO

GGPIOG4GPIOG5C28x

GPIO

Pin

Assignment/GPIOF14

XF7

-16C28x

GPIO

Functional

Block

Diagram•0

• •

1MUX

Control

Bit0

=

I/O

Function1

=

Primary

FunctionPrimaryPeripheralFunctionI/O

DATBit

(R/W)I/O

DIR

Bit0

=Input1=OutputGPxMUXGPxDIRGPxDATGPxSETGPxCLEARGPxTOGGLE 15

-

8

7

-0QUALPRDGPxQUAL00h01hno

qualification

(SYNC

to

SYSCLKOUT)QUALPRD

=

SYSCLKOUT/2FFhQUALPRD

=

SYSCLKOUT/5100.2.h.QUAL.PRD

=

SYSCL.KOUT/4.

.Input

Qualification7

-17；，；7

-18SPI-A

FIFO

Transmit

RegisterTXFFINTTXFFINTCLRTXFFIENTXFFIL4TXFFIL3TXFFIL2TXFFIL1TXFFIL0SPIFFENTXFIFORESETTXFFST4TXFFST3TXFFST2TXFFST1TXFFST0SPIFFTX

@

0x00704ATX

FIFO

Status

(read-only)TX

FIFO

Interrupt

LevelSPI

FIFOEnhancementsTX

FIFO

ResetTX

FIFOInterrupt(on

match)EnableTX

FIFOInterruptFlag

(read-only)TX

FIFOInterruptFlag

Clear7

-19SPI-A

FIFO

Receive

RegisterSPIFFRX

@

0x00704BRXFFINTRXFFINTCLRRXFFIENRXFFIL4RXFFIL3RXFFIL2RXFFIL1RXFFIL0RXFF-OVFRXFF-OVF

CLRRXFIFORESETRXFFST4RXFFST3RXFFST2RXFFST1RXFFST0RX

FIFO

Status

(read-only)RX

FIFO

Interrupt

LevelRX

FIFO

ResetRX

FIFOInterrupt(on

match)EnableRX

FIFOInterruptFlag

(read-only)RX

FIFOInterruptFlag

ClearRX

FIFOOverflowFlag

(read-only)RX

FIFOOverflowFlag

Clear7

-20SPI

FIFO

控制寄存器（SPIFFCT

）地址704Ch158R-076543210FFTXDL