文本fpga2018会议特别

1、FPGA2018 SpecialSessionDeepLearning BitaDarvishRouhani,mmadGhasemzadeh,FarinazCausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs.1-10ShuoWang,ZheLi,CaiwenDing,BoYuan,QinruQiu,YanzhiWang,YunC-LSTM: Enabling Efficient LSTM using Structured Compression Tec

2、hniques on ChangGao,DanielNeil,EneaCeolini,Shih-ChiiLiu,TobiDelbrckDeltaRNN: A Power-efficient Recurrent Neural Network Accelerator.21-HirokiNakahara,HaruyoshiYonekawa,TomoyaFujii,ShimpeiALightweightYOLOv2:ABinarizedwithAParallelSupportVectorRegressionfor an FPGA.31-40Session1:Architecture1StephenM.

3、Williams,MingjieArchitectureandCircuitDesignofl-SpintronicFPGA.41-YueZha,JingLiquid Silicon: A Dentric Reconfigurable Architecture Enabled by RRAM WenyiFeng,JonathanW.Greene,AlanImprovingFPGrformancewithaS44LUTStructure.61-Session ChinHauHoo,AkashParaDRo: A Parallel Deterministic Router Based on Spa

4、tial Partitioning and Soheiljer,ZhihengWang,KiaRoutingMagic:PerformingComputationsUsingRoutingNetworksandVotingLogicon Unary Encoded Data.77-86ShenghsunCho,MrunalPa,HanChen,MichaelFerdman,PeterA Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected Session3:DeepJunzhongShen,YouH

5、uang,ZelongWang,YuranQiao,MeiWen,ChunyuanTowards a Uniform Template-based Architecture for Accelerating 2D and 3Dson Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong: A Cus

6、tomizable Matrix Multiplication Framework for the In HARPv2 Xeon+FPGAPlatform:ADeepLearningCaseStudy.107-HanqingZeng,RenChen,ChiZhang,ViktorK.AFrameworkf eneratingHighThroughput ImplementationsonFPGAs.117-Session4:HighLevelSynthesis4LanaJosipovic,RadhikaGhosal,PaoloDynamically Scheduled High-level S

7、ynthesis.127-SteveDai,GaiLiu,ZhiruAScalableApproachtoExactResource-ConstrainedSchedulingBasedonaJointSDC and SAT Formulation.137-146JefersonSantiagodaSilva,Franois -RaymondBoyer,J.M.PierrepatibleHigh-LevelSynthesisofLowLatency100Gb/sStreamingPacketParsers in FPGAs.147-152Session5:Applications1 5Hami

8、dRezaZohouri,ArturPodobas,SatoshiCombinedSpatialandTemporalBlockingforHigh-PerformanceStencilComputationon FPGAs Using OpenCL.153-162JanDrre , Dario Paradzik, Holger A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on GregStitt,AbhayGupta,MadisonN.Emas,DavidWilson,Austi

9、nScalable Window Generation for the In Broadwell+Arria 10 and High-Bandwidth FPGA Systems.173-182Martin Langhammer, Bogdan High-Performance Session6:HighLevelSynthesis6Ho-CheungNg,ShuanglongLiu,WayneJuanEscobedo,MingjieGraph-TheoreticallyOptimalMemoryBankingforStencil-BasedComputingKernels.199- Al-S

10、hahnaJamal,JeffreyGoeders,StevenJ.E. Session7:CircuitsandComputation JialiangZhang,JingDegree-awareHybridGraphTraversalonFPGA-HMCPlatform.229-SorooshKhoram,JialiangZhang,MaxwellStrange,JingAcceleratingGraphytics byCo-OptimizingStorageandAccessonanFPGA-HMC Session 8:Applications 8JakubCabal,PavelBenc

11、ek ,LukasKekely,MichalKekely,ViktorPus,JanConfigurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed ShijieZhou,RajgopalKannan,YuMin,ViktorK.FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish

12、Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wen Wang, Zhiru Zhang:Rosetta: A Realistic High-Level Synthesis Benark Suite for Software Programmable SeanFox,DavidBoland,PhilipHengWaiFPGA Fastfood - A High Speed Systolic Implementation of a Lar

13、ge Scale Online Kernel PosterSession1ZhemingJin,KazutomoOptimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only).285RuizheZhao,XinyuNiu,WayneAutomatic Optimising with Depthwise Separable Convolution on FPGA: KenichiKoizumi,KeiHiraki,MaryContinuous Skyli

14、ne Computation Accelerator with Parallelizing Dominance Relation Calculations: (NachiketKapre,TusharFastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts ( YuzeChi,PeipeiZhou,JasonAnOptimalMicroarchitectureforStencilComputationwithDataReuseandFine-Grained Parallelism: (HaiyueSong,Xia

15、ngSong,TianjianLi,HaoDong,NaifengJing,XiaoyaoLiang,LiA FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Shumarayev, Aravind I

16、n-Package -Specific ASICs for In Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(ZhemingJin,HalEvaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (JasonCong,ZhenmanFang,YaoHu,DiK-Flow: A Programming and Scheduling Framework t

17、o Optimize Dataflow Execution on CPU-FPGA Platforms: (ZheChen,AndrewHowe,HughT.Blair,JasonFPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: ( JasonCong,ZhenmanFang,MichaelLo,HanruiWang,JingxianXu,ShaochongUnderstandingPerformanceDifferencesofFPGAsandGPUs:(AbtractPosterSession2-NanDin

18、g,WeiZhang,YanhuaMa,ZhenguoSoftware/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: JuexiaoSu,LeiSolvingSatisfiabilityProblemonQuantumAnnealer:ALessonfromFPGACADTools: ChongchongXu,ChaoWang,YiweiZhang,LeiGong,XiLi,XuehaiDomino: An Asynchronous and Energy-efficient Accelerator fr

19、aph Processing: MinghuaShen,WentaiZhang,NongXiao,GuojieTowards Serial-Equivalent Parallel Routing for FPGAs: Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: ( MinghuaShen,JiaxiZhang,NongXiao,

20、GuojieBoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: GaiLiu,EcenurUstun,ShaojieXiang,ChangXu,GuojieLuo,ZhiruDATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (WentaiZhang,JiaxiZhang,MinghuaShen,NongXiao,GuojieMapLarge-Scale

21、DNNsonAsymmetricFPGAs:YankangDu,QinrangLiu,ShuaiWei,ChenSoftware-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: DaisukeSuzuki,TakahiroDesign of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Weikang Qiao, Jieqio

22、ng Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: PosterSession3 FadyHussein,LukaDaoud,NaderHexCell:aHexagonalCellforEvolvableSystolicArraysonFPGAs:XiaoyuYu,DongPerformance Comparison of Multiples and Detection with Imager-driven Processing Mode for Ultrafast-Imager: (ShuanglongLiu,XinyuNiu,WayneA Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA:MikhailAsi