Verilog数字系统设计教程-总结

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3、等教育 HYPERLINK /list/10 HYPERLINK /list/109 工学1.11 module and_logic(a,b,c);5assign c=a&b;6 endmoduleverilog12-51.121 module (123.)1131 module and_logic(2345 );41 my_and_logic and_logic(input_a,input_b,output_c);“.” 5my_and_logic and_logic(.a(input_a),5);1.2I/O1233I/Oinputinput-1:011.2.21.“assign”152.

4、and#2ul(q,a,b);3.“always6end”assign“always” 2.11.bBdDhHoO2.xzxzz“”3.-8d52.2.2“parameter”72.2verilogwirereg 1reg n-1:0 name_1,name_2,name_3,.name_i;verilogregRAMROMreg1reg n-1:0 RAMm-1:0;/mnmemory3.3.1!3.2=zx“x”!=3.3anan04B10011=5B100103.4 :C=&B;:1C=(B0&B1)&B2)&B3;.2b=a;.1begin_end1.2

5、.1.verilog2;end/join 4.4.1initialalwaysbeginend121else4out1 = int2;3out1 = int3;4.2case 4516d0: result = 10b01_1111_1111;16d1: result = 10b01_1111_1110;1011 endcasecasecasezcasexzx4.31 foreverend1 repeat(n)end ;endcfor(1;2;3)4.4begin-endbeginx = 1b0;910end fork-join45fork6x = 1b0;78910

6、join5.Verilog44.function5.1initialendinitial0ns5.2alwaysalways “(posedgeclkornegedgereset_norcount)” (posedgeclk)(negedgereset_n)(count)“or”“,”“”“”always (reset,clock,d)beginif(reset)q = 1b0;7end“(*)*5.3taskfuntiontaskfunction3.endtask endendfunctionfunction 7:0 getbyte;input 15:0 address;begingetbyte = result_expression;end/endfunction3.4.5