超大规模集成电路

1、Assignment 41. Using HSPICE and TSMC 0.18 pm CMOS technology model with 1.8 V power supply, plot the subthreshold current IDSUB versus VBS，and the saturation current IDSAT versus VBS for an NMOS device with W=400 nm and L=200 nm. Specify the range for VBS as 0 to 2.0 V. Explain the results.2. Using

2、HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, (1) plot log IDS versus VGS while varying VDS for an NMOS device with L=200 nm, W=800 nm and a PMOS with L=200 nm, W= 2 pm. (2) Which device exhibits more DIBL(Drain-Induced Barrier Lowering)?1、 solution：Codel：*.title Idsub Vs Vb

3、s .lib C:UsersAdministratorDesktopIdsubmm018.l TT * set 0.18um library.opt scale=0.1u * set lambda*.model nch NMOS level=49mn drainn gaten Gnd bodyn nch l=2 w=4 ad=20 pd=4 as=20 ps=4Vdd Vdd 0 1.8Vdsn drainn 0 0.2Vgsn gaten 0 0.2Vbsn bodyn Gnd 1.8 .dc Vbsn 0 -2.0 -0.05 .print dc I1(mn) .enddsatversus

4、 VBS:Code2：*.title Idsat_Vs_Vbs.lib C:UsersAdministratorDesktopIdsubmm018.l TT * set 0.18um library.opt scale=0.1u * set lambda*.model nch NMOS level=49mn drainn gaten Gnd bodyn nch l=2 w=4 ad=20 pd=4 as=20 ps=4Vdd Vdd 0 1.8Vdsn drainn 0 14Vgsn gaten 0 1.8Vbsn bodyn Gnd 1.8.dc Vbsn 0 -2.0 -0.05.prin

5、t dc I1(mn).end上早对数化坐标下：其中红色表示NMOS器件，黄色表示PMOS器件。LjLj司A颇！盹 j、 1j.2WLEy I IJ喊皿别Code:*.title Ids_Vs_Vgs.param supply=1.8 *set value of Vdd.lib C:UsersAdministratorDesktopIds_Vgsmm018.l TT * set 0.18um library.opt scale=0.1u * set lambda*.model pch PMOS level=49*.model nch NMOS level=49mp drainp gatep V

6、dd Vdd pch l=2 w=20 ad=100 pd=20 as=100 ps=20mn drainn gaten Gnd Gnd nch l=2 w=8 ad=40 pd=8 as=40 ps=8Vdd Vdd 0 SupplyVgsp Vdd gatep dcVgsn gaten 0 dcVdsp Vdd drainp dcVdsn drainn 0 dc.dc Vgsp 0 Supply Supply/40 Vdsp 0 Supply Supply/8.dc Vgsn 0 Supply Supply/40 Vdsn 0 Supply Supply/8.print dc I1(mp).print dc I1(mn).end(2) DIBL即是当沟道长度减小、电压VGS增加、使得漏结与源结的耗尽层靠近时，沟道中 的电力线可以从漏