数字图像处理系统DM642介绍资料

1、High-Performance Digital Media Processor (TMS320DM642) 500-, 600-MHz Clock Rate Eight 32-Bit Instructions/Cycle 4000, 4800 MIPS Fully Software-Compatible With C64x.TMS320DM642VelociTI.2. Extensions to VelociTI.Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x. DSP Core Eight Highly Independent F

2、unctional Units With VelociTI.2. Extensions: Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-Bit Multiplies(32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies(16-Bit Results) per Clock Cycle Load

3、-Store Architecture WithNon-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional共二十七页Instruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation,

4、 Bit-Counting VelociTI.2. Increased Orthogonality2级CACHE数量(shling)不同与 TMS320C6416L1/L2 Memory Architecture 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped) 128K-Bit (16K-Byte) L1D Data Cache(2-Way Set-Associative) 2M-Bit (256K-Byte) L2 Unified MappedRAM/Cache (Flexible RAM/Cache Allocation)共二十七页

5、C64X DSP 核心(hxn)共二十七页64-Bit External Memory Interface (EMIF) Glueless Interface to AsynchronousMemories (SRAM and EPROM) andSynchronous Memories (SDRAM,SBSRAM, ZBT SRAM, and FIFO) 1024M-Byte Total Addressable ExternalMemory Space外挂存储器极限(jxin)空间比DAM6416小共二十七页10/100 Mb/s Ethernet MAC (EMAC) IEEE 802.3

6、 Compliant Media Independent Interface (MII) 8 Independent Transmit (TX) and8 Independent Receive (RX) Channels直接(zhji)以太网集成共二十七页Three Configurable Video Ports Providing a Glueless I/F to CommonVideo Decoder and Encoder Devices Supports Multiple Resolutions andStandards Supports RAW Video I/O Transp

7、ort Stream Interface Mode直接图象(t xin)接口不同与TMS320C6416VCXO Interpolated Control Port (VIC) Supports Audio/Video SynchronizationHost-Port Interface (HPI) 32-/16-Bit32-Bit/66-MHz, 3.3-V Peripheral ComponentInterconnect (PCI) Master/Slave InterfaceConforms to PCI Specification 2.2主机接口与MS320C6416相同(xin tn

8、)，速度快共二十七页图象(t xin)接口的细节共二十七页Three Configurable Video Ports Providing a Glueless I/F to CommonVideo Decoder and Encoder Devices Supports Multiple Resolutions andStandards Supports RAW Video I/O Transport Stream Interface Mode图象接口(ji ku)的细节共二十七页Enhanced Direct-Memory-Access (EDMA)Controller (64 Indep

9、endent Channels)Management Data Input/Output (MDIO)单独(dnd)与TMS320C6416的多通道音频串口Multichannel Audio Serial Port (McASP) Eight Serial Data Pins Wide Variety of I2S and Similar BitStream Format Integrated Digital Audio I/F TransmitterSupports S/PDIF, IEC60958-1, AES-3,CP-430 FormatsInter-Integrated Circu

10、it (I2C) BusThree 32-Bit General-Purpose TimersFlexible PLL Clock GeneratorSixteen General-Purpose I/O (GPIO) Pins共二十七页多通道音频(ynpn)串口共二十七页Two Multichannel Buffered Serial PortsIEEE-1149.1 (JTAG)Boundary-Scan-Compatible548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch548-Pin Ball G

11、rid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch0.13-m/6-Level Cu Metal Process (CMOS)3.3-V I/Os, 1.2-V Internal (-500)3.3-V I/Os, 1.4-V Internal (-600)多通道串口共二十七页MIPS1200-24004800-8800Code size reductionAdvanced instruction packingImagingGeneralSpecial purposeinstructionsCommunicationsGeneral

12、Special purposeinstructions8-bit MMACs300-60016-bit MMACs300-6008x16x2400-44004800-88008x15x25%MHz150-300 600-1100VelociTITM C62xTMVelociTI.2TM C64xTMImprovement 4x4xOverall PerformanceTMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI.very-long-instruct

13、ion-word (VLIW) architecture (VelociTI.2.) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. 一代(y di)、二代的差别10X共二十七页类型格式分辨率帧频HZbit/像素比特率Mb/s电视电话QCIF176*14429.97129.1会议电视CIF352*28829.971236.4常规电视ITU-R601720*5762516165.9HDTVITU-R7091920*115225168

14、84.7类型带宽KHZ采样率KHZ比特/样点比特率kb/s电话语音0.23.481296宽带语音0.0571614224调频广播0.02153216512CD光盘0.012044.116705.6DAB/DAT0.01204816768图像压缩的必要性语音(yyn)压缩的必要性共二十七页共二十七页共二十七页xDSL modemsPooled modems、3G基站无线以太网企业交换机 PBX,ATM多路语音识别多媒体网关网络摄像机安全认证二维或三维条形码识别高速打印机网络设备开发平台图像实时监控图像采集、压缩、视频输出高速实时数据(shj)采集与处理雷达信号处理软件无线电医疗设备视频(shpn

15、)监控顶置盒Medical Imaging共二十七页The DM642 DSP possesses the perational flexibility of high-speed controllers and the numerical capability of array processors.适合(shh)的应用The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bi

16、t MACs per cycle for a total of 4800 MMACS. The速度(sd)计算关系The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache.第一级CACHE直接MAPThe Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between p

17、rogram and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.第二级CACHE可以灵活配置共二十七页The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VI

18、C); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (P

19、CI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.多功能辅助(fzh)外围设备共二十七页The DM642 device has three co

20、nfigurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. All three Video Port peripherals have the capability to operate as a video-capture port, a video-display port, or a transport stream interface

21、 (TSI) capture port. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITUBT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).适合(shh)各个标准These three video port peripherals are configurable and can support either video capture and/or video display modes

22、. Each video port consists of two channels A and B with a 5120-byte capture/display buffer that is splittable between the two channels.视频(shpn)端口功能For capture operation, the video port can operate as two 8/10-bit channels of BT.656 or two 8/10-bit channel of raw video capture; or as a single channel

23、 of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI.视频组合使用共二十七页For display operation, the video port can operate as a single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit ra

24、w video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the TMS320DM642 Technical Overview (literature number SPRU615) o

25、r the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).视频输出组合(zh)配置BT.656-3 defines a schema for the digital interconnection of television video signals in conjunction BT.1120-1 - Digital interfaces for 1125/60 and 1250/50 HDTV studio signalsSMPT

26、E 125M (was RP 125) The SMPTE recommended practice for bit-parallel digital interface for component video signals. SMPTE 125M defines the parameters required to generate and distribute component video signals on a parallel interface.共二十七页CCIR Rec. 601 (last version is 601-2) specifies the the image

27、format, acquisition semantic, and parts of the coding for digital standard television signalsCCIR-601 gives the specification for encoding of 4:2:2 signals and a tentative specification of 4:4:4 encoding. 4:2:2 means, that the color-difference signals Cr and Cb are sampled with half of the sampling

28、frequency of the luminance signal Y, that is 13.5MHz to 6.75MHz. It also specifies the number of samples per line for 525/60(59,94) systems and 625/50 systems. The samples per total line are different, but the samples per active line are the same for both systems: 720 samples per active line CCIR601

29、跟我们的6416演示程序(chngx)关系比较大共二十七页DM642-EVM的配置(pizh)要求Supported Operating SystemsMicrosoft Windows 98. (SP1 and SE)Microsoft Windows NT. (SP6)Microsoft Windows 2000. (SP1 and SP2)Microsoft Windows XP. (Home and Professional)Code Composer Minimum Requirements233 MHz or faster Pentium or compatible600 Mb f

30、ree hard disk space64 Mb free RAMSVGA (800 x600) color displayCD-ROM drive共二十七页DM642-EVM功能(gngnng)框图共二十七页32 Mb of SDRAM4 Mb of linear Flash memory2 video decoders1 video encoderOn-Screen Display FPGA implementationDual RS-232 UARTs and line driversAIC23 stereo codec10/100 Ethernet PHY32 Kb I2C EEPROM8 programmable LEDsNumerous video inputs and outputsSupport for HDTV data ratesDM642-EVM功能(gngnng)特征共二十七页The heart o