超大规模集成电路第四次作业2016秋,段成华

1、1. Shown below are buffer-chain designs.(1) Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1.Solution:由题可知：F =64根据经验fog =3.6为最合适的值，所以f = N乒= N64 = 3.6,所以N =3.24，但是级数必须为整数所以取N =3 ,又因为=1 ,所以:=3父(1 +V64) =15 ,所以f =4时最合适 Using HSPICE and TSMC 0.18 um CMOS tec

2、hnology model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent parameters of N, f, andptSolution:根据(1)中计算知道三级最合适，所以验证如下：A)、一级无负载测本征延时代码如下：.title buffer-chain 1.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u *

3、 set lambda.options post=2 list.temp 27.global vddVdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100n 频率为 10MhzCl vout gnd 0f $Cg1=2.46fF,负载为 CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad

4、=wp*t pd=wp+2*t as=wp*t ps=wp+2*t .endsX1 vin vout inv wn=3.5 wp=10 t=7.5.op.tran 5p 5n.meas tran voutmax max v(vout) from=5p to=5n.meas tran voutmin min v(vout) from=5p to=5n$一级.meas tran tphll+trig v(vin)+val=0.9+rise=1+targ v(vout)+val=0.5*(voutmax-voutmin)+voutmin+fall=1.meas tran tplh1+trig v(v

5、in)+val=0.9+fall=1+targ v(vout)+val=0.5*(voutmax-voutmin)+voutmin+rise=1.end一级无负载测得本征延时约为17ps；SOURCE= HSPICE VERS工OlM D-2010. 03-SPL 32-BIT.T1TLE ?. title Luffer-ohain L?Ycrutw芯Youtinintphlltplhlteniperal ter#2.2321-0. 24屋1.725E-1LL 703e-ll.27.000012)带上64倍Cg1大小的负载测得延时为750.35ps,是本征延时的44倍JDATAl SOURCE

6、= HSPICEJ VERSION D-2010.03-SP1 32-BIT TITLE J,title bufferchain Vvoutmaxvoutwintphlltplhlteinperalter#8023-4. 476e-037. 059e-107. 943e-102T, 0000LB)、三级带负载测延时代码如下：.title buffer-chain 3.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u * set lambda.options post=2

7、 list.temp 27.global vdd.param fan=4Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100nCl vout gnd 0f $Cg1=2.46fF,负载为 CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad=wp*t pd=wp+2*t as=wp*t

8、ps=wp+2*t .endsX1 vin 2 inv wn=3.5 wp=10 t=7.5X2 23 inv wn=fan*3.5 wp=fan*10 t=5X3 3 vout inv wn=fan*fan*3.5 wp=fan*fan*10 t=5.op.tran 50p 500n.meas tran voutmax max v(vout) from=50p to=500n.meas tran voutmin min v(vout) from=50p to=500n$三级.meas tran tphl3+trig v(vin)+val=0.9+rise=1+targ v(vout)+val

9、=0.5*(voutmax-voutmin)+voutmin+fall=1.meas tran tplh3+trig v(vin)+val=0.9+fall=1+targ v(vout)+val=0.5*(voutmax-voutmin)+voutmin+rise=11)带上64倍Cg1大小的负载测得延时为174.6ps,是本征延时的10.27倍$DATA1 SOURCE HSPICE VRSION D-2010- O3-SP1 32-BIT.TITLE . title buff er - chai n 3/ voutmaicvoutmintphlStplhSteirperal t ex#1.

10、8449-6. HSe-02L 69赳TO1. 794e-1027, 00001总结如下：经过调整参数近似时每一级的=1,所以经过手工计算得到一级带负载和三级带负载的延时比值为：/= 153 =0.2344,而仿真得到的结果为tp1 65tp0同理其他级的延时代码也是如上的及皂=0.2327 ,所以符合手工计算的比值, 750.35写法，经过仿真得到三级延时最小。.endConsider the logic network below, which may represent the critical path of a more complex logic block. The output

11、 of the network is loaded with a capacitance which is 5 times larger than the input capacitanceof the first gate, which is a minimum-sized inverter. The effective fanout of the path hence equals F = C/Cg1 =5.-J-5TUsing HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a c

12、ircuit simulation scheme to verify the OPTIMAZATION parameters ofg, f, and s for each of the inverter and gates.Solution:由题得到路径逻辑努力G=1M5M5黑1=竺，由于没有分支 B=1,所以99H =GFB =125,所以使延时最小的逻辑努力为 卜=炳=4口25=1.93,得至IJ如下 的扇出系数：f1 =1.93, f2 =1.16, f3 =1.16, f4 =1.93,利用书上公式6.18计算得到尺寸系数 S =1$ = Gg /g2 =1.16 = f1 f2& /

13、g3 =1.34,S4 = f f23。/g4 = 2.6。电路仿真代码如下：.title INV 2NAND 2NOR.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library .options post=2 list.temp 27.global vddVdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600pC1 vout gnd 12.3f $Cg1=2.46fF,所以负载为 12.3fF.subckt inv1 in out wn

14、=0.35u wp=1u t=0.75umn out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t .ends.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u*1.16 wp=1u*1.16t=0.5u $优化尺寸系数 S2*.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn

15、=0.35u wp=1ut=0.5u$未优化尺寸系数S2mn3 NAND-S2 NAND-C1 gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn2 NAND-S1 NAND-B1 NAND-S2 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn1 NAND-D1 NAND-A1 NAND-S1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp1 NAND-D1 NAND-A1 vdd vdd

16、 PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*tmp2 NAND-D1 NAND-B1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*tas=wp*t ps=wp+2*tvdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*tmp3 NAND-D1 NAND-C1 vdd as=wp*t ps=wp+2*t .ends .subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u*1.34 wp=1u*1.34 t=0.5u$优化尺寸系数S3*.subckt no

17、r2 NOR-A1 NOR-D1$未优化尺寸系数S3mn2 NOR-D1 NOR-B1 gnd gnd as=wn*t ps=wn+2*tmn1 NOR-D1 NOR-A1 gndgndas=wn*t ps=wn+2*tmp1 NOR-S1 NOR-A1 vddvddas=wp*t ps=wp+2*tmp2 NOR-D1 NOR-B1 NOR-S1 vdd as=wp*t ps=wp+2*tNOR-B1 wn=0.35u wp=1u t=0.5uNCH l=0.2u w=wnNCH l=0.2u w=wnPCH l=0.2u w=wpPCH l=0.2u w=wpad=wn*t pd=wn+2

18、*tad=wn*t pd=wn+2*tad=wp*t pd=wp+2*tad=wp*t pd=wp+2*t$优化尺寸系数S4.ends.subckt inv2 in out wn=0.35u*2.6 wp=1u*2.6 t=0.5u *.subckt inv2 in out wn=0.35u wp=1u t=0.5u $未优化尺寸系数 S4 mn out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*t mp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*

19、t ps=wp+2*t .endsX1 vin 2inv1X2 23vddvdd nand3X3 34gndnor2X4 4voutinv2.op.tran 5p 3000p.meas tran voutmax max v(vout) from=5p to=3000p.meas tran voutmin min v(vout) from=5p to=3000p.meas tran tphl+trig v(vin)+val=0.9 +rise=2+targ v(vout)+val=0.5*(voutmax-voutmin)+voutmin+rise=2.meas tran tplh+trig v(vi