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1、Verification ContinuumHAPS PrototypingUser GuideSeptember 2021Synopsys Confidential InformationPreface 2021 Synopsys, Inc. 2HAPS Prototyping User GuideSeptember 2021Synopsys Confidential InformationCopyright Notice and Proprietary Information 2021 Synopsys, Inc. This Synopsys software and all associ
2、ated documenta- tion are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibit
3、ed.Free and Open-Source Licensing NoticesIf applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America
4、. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them.DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
5、 MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.TrademarksSynopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at HYPERLINK /Company/Pages/Trademarks.aspx /Company/Pages/Trademarks.aspx.All other
6、 product or company names may be trademarks of their respective owners.PrefaceThird-Party LinksAny links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practice
7、s, availability, and content.Synopsys, Inc.690 East Middlefield Road Mountain View, CA 94043 HYPERLINK / September 2021HAPS Prototyping User Guide 2021 Synopsys, Inc.September 2021Synopsys Confidential Information3Preface 2021 Synopsys, Inc. 4HAPS Prototyping User GuideSeptember 2021Synopsys Confide
8、ntial InformationHAPS Prototyping User Guide September 2021 2021 Synopsys, Inc.5Synopsys Statement on Inclusivity and DiversitySynopsys is committed to creating an inclusive environment where every employee, customer, and partner feels welcomed. We are reviewing and removing exclusionary language fr
9、om our products and supporting customer-facing collateral. Our effort also includes internal initiatives to remove biased language from our engineering and working environment, including terms that are embedded in our software and IPs. At the same time, we are working to ensure that our web content
10、and software applications areusable to people of varying abilities. You may still find examples of non-inclu- sive language in our software or documentation as our IPs implement industry-standard specifications that are currently under review to remove exclusionary language.Contents HYPERLINK l _boo
11、kmark0 Chapter 1: Starting with FPGA-Based Prototyping HYPERLINK l _bookmark1 Introduction to FPGA-Based Prototyping16 HYPERLINK l _bookmark3 About the HAPS Prototyping Solution16 HYPERLINK l _bookmark6 HAPS ProtoCompiler and ProtoCompiler DX Functionality17 HYPERLINK l _bookmark7 HAPS ProtoCompiler
12、 Design Flows19 HYPERLINK l _bookmark10 HAPS ProtoCompiler DX Design Flows22 HYPERLINK l _bookmark12 HAPS Prototyping and Standard Prototyping Use Models24 HYPERLINK l _bookmark20 Starting the Tool27 HYPERLINK l _bookmark36 Chapter 2: Converting ASIC Designs to FPGA HYPERLINK l _bookmark40 Getting A
13、SIC Designs Ready for FPGA34 HYPERLINK l _bookmark46 Dividing up the Design36 HYPERLINK l _bookmark47 Handling I/O Pads37 HYPERLINK l _bookmark49 Handling User-Defined Primitives37 HYPERLINK l _bookmark50 Converting ASIC Memories38 HYPERLINK l _bookmark53 Making ASIC Netlists Suitable for FPGA Desig
14、n41 HYPERLINK l _bookmark55 Converting ASIC Clocks42 HYPERLINK l _bookmark59 General Guidelines for ASIC Clocks42 HYPERLINK l _bookmark60 Defining Clocks44 HYPERLINK l _bookmark70 Scaling External Clock Speed48 HYPERLINK l _bookmark71 Dealing with IP54 HYPERLINK l _bookmark76 Working with Power Spec
15、ifications55 HYPERLINK l _bookmark80 Converting Constraints56 HYPERLINK l _bookmark82 Checking Resources56 HYPERLINK l _bookmark86 Chapter 3: Creating and Compiling Databases HYPERLINK l _bookmark88 Working with a Design Database58 HYPERLINK l _bookmark91 Creating a Design Database58 HYPERLINK l _bo
16、okmark96 Loading and Navigating Database States62 HYPERLINK l _bookmark105 Converting Legacy Projects to Databases65 HYPERLINK l _bookmark109 Archiving and Unarchiving Databases66 HYPERLINK l _bookmark120 Compiling the Design77 HYPERLINK l _bookmark129 Compiling with the run compile Command80 HYPERL
17、INK l _bookmark133 Running Diagnostic Compiler Mode85 HYPERLINK l _bookmark137 Running Fast Compiler Mode (Standard Compiler)86 HYPERLINK l _bookmark143 Using Different Standard Compiler Modes Together87 HYPERLINK l _bookmark146 Running Bottom-Up Compile90 HYPERLINK l _bookmark150 Controlling the Co
18、mpiler Run with Options and Constraints92 HYPERLINK l _bookmark179 Adding Design Files96 HYPERLINK l _bookmark181 Specifying Source Files (Standard Compiler)97 HYPERLINK l _bookmark183 Specifying Source Files Using a Command Argument97 HYPERLINK l _bookmark189 Creating a Text File List of Source Fil
19、es101 HYPERLINK l _bookmark195 Specifying Source Files from the GUI103 HYPERLINK l _bookmark196 Checking for Unused Files105 HYPERLINK l _bookmark197 Using Variables in File Paths105 HYPERLINK l _bookmark199 Specifying Verilog Standards107 HYPERLINK l _bookmark206 Using UUM and Group Mapping109 HYPE
20、RLINK l _bookmark213 Creating an lmf File110 HYPERLINK l _bookmark220 Setting Library Options with -hdl_define114 HYPERLINK l _bookmark232 Using Unified Compile120 HYPERLINK l _bookmark234 Unified Compile Design Flow120 HYPERLINK l _bookmark235 Running Unified Compile121 HYPERLINK l _bookmark238 Pre
21、paring the Input for Unified Compile125 HYPERLINK l _bookmark240 Setting up the RTL Design Files and Library Mapping127 HYPERLINK l _bookmark243 Setting up the UTF File and the VCS Script128 HYPERLINK l _bookmark246 Including IPs in a UC Design130 HYPERLINK l _bookmark252 Including Complex SystemVer
22、ilog Port Modules133 HYPERLINK l _bookmark253 Checking the UC Database135 HYPERLINK l _bookmark254 Running zFmCheck to Validate VCS Design Files135 HYPERLINK l _bookmark256 Running Lint Checks with VC Static137 HYPERLINK l _bookmark257 Checking for CDC Violations with VC Static139 HYPERLINK l _bookm
23、ark261 Compiling Incrementally145 HYPERLINK l _bookmark262 Design Database to SRS Incremental Flow (UC)145 HYPERLINK l _bookmark263 Compiling Incrementally Using Bypass Flow (UC)147 HYPERLINK l _bookmark266 Compiling Incrementally Using Structural VM (UC)157 HYPERLINK l _bookmark267 Using the Bypass
24、 Flow (Standard Compiler)160 HYPERLINK l _bookmark271 Specifying Constraints162 HYPERLINK l _bookmark272 Adding Constraints to a Design Database162 HYPERLINK l _bookmark273 Specifying Directives in a CDC File163 HYPERLINK l _bookmark280 Setting Options166 HYPERLINK l _bookmark292 Chapter 4: Partitio
25、ning the Design HYPERLINK l _bookmark293 Overview of Partitioning172 HYPERLINK l _bookmark295 The Partitioning Flow172 HYPERLINK l _bookmark297 Design Methodology for Partitioning173 HYPERLINK l _bookmark302 Setting up Files for Partitioning177 HYPERLINK l _bookmark305 Defining the System in a TSS F
26、ile178 HYPERLINK l _bookmark309 Exploring Partition Choices with a Basic TSS179 HYPERLINK l _bookmark314 Defining the Target System in a Detailed TSS File183 HYPERLINK l _bookmark323 Defining Clocks in the TSS File188 HYPERLINK l _bookmark326 Defining Hardware Interconnect190 HYPERLINK l _bookmark32
27、7 Defining Connections with Auto-Cabling191 HYPERLINK l _bookmark331 Defining Connections with board_system_create -interconnect194 HYPERLINK l _bookmark336 Defining Daughter Boards198 HYPERLINK l _bookmark372 Moving from Abstract PCF to TSS: Flow Example214 HYPERLINK l _bookmark377 Validating TSS C
28、able Connections with conspeed_hstdm219 HYPERLINK l _bookmark378 Validating the TSS Against the Hardware220 HYPERLINK l _bookmark381 Generating TSS Files Using TSS Builder222 HYPERLINK l _bookmark382 Choosing Systems and Daughter Boards223 HYPERLINK l _bookmark383 Chaining CDEs226 HYPERLINK l _bookm
29、ark384 Assigning Clocks227 HYPERLINK l _bookmark385 Assigning Top IO229 HYPERLINK l _bookmark386 Connecting Cables Within and Across Systems230 HYPERLINK l _bookmark387 Connecting Daughter Boards231 HYPERLINK l _bookmark388 Generating TSS Files232 HYPERLINK l _bookmark389 Defining Constraints in PCF
30、 Files235 HYPERLINK l _bookmark394 Using Abstract PCF Commands for Partition Exploration236 HYPERLINK l _bookmark396 Specifying PCF Constraints for Partitioning239 HYPERLINK l _bookmark408 Specifying PCF Constraints in the PCF Editor (GUI)248 HYPERLINK l _bookmark409 Using PCF Queries for TSS and Ne
31、tlist Information254 HYPERLINK l _bookmark412 Manually Assigning Inter-FPGA Nets to Traces258 HYPERLINK l _bookmark417 Working Iteratively with PCF Assignments260 HYPERLINK l _bookmark418 Working with HAPS Systems262 HYPERLINK l _bookmark420 Working with HAPS Global Clocks262 HYPERLINK l _bookmark43
32、7 Assigning and Distributing HAPS-80 Reset271 HYPERLINK l _bookmark442 Defining HAPS-80 Hardware276 HYPERLINK l _bookmark451 Defining a HAPS-DX7 System as a Subsystem282 HYPERLINK l _bookmark455 Defining HAPS-80 Desktop Single/Dual (HAPS-80D)284 HYPERLINK l _bookmark459 Working with HAPS-100 Modules
33、289 HYPERLINK l _bookmark460 Working with HAPS-100 Clocks289 HYPERLINK l _bookmark471 Generating Controlled Clocks using HAPS Clock Generator301 HYPERLINK l _bookmark473 Working with HAPS-100 Resets312 HYPERLINK l _bookmark475 Using UMRBus 3.0 with HAPS-100 Modules313 HYPERLINK l _bookmark477 Using
34、run pre_partition to Define Partitions317 HYPERLINK l _bookmark481 Partitioning the Logic321 HYPERLINK l _bookmark483 Using run partition to Create Partitions322 HYPERLINK l _bookmark487 Partitioning Single-FPGA Designs328 HYPERLINK l _bookmark489 Working with Area Estimates for Partitioning330 HYPE
35、RLINK l _bookmark495 Using Timing-Aware Partitioning334 HYPERLINK l _bookmark503 Optimizing Multi-Hop Paths337 HYPERLINK l _bookmark512 Partitioning Clocks341 HYPERLINK l _bookmark526 Locking Down Partitions345 HYPERLINK l _bookmark530 Using Interactive Partitioning348 HYPERLINK l _bookmark532 Analy
36、zing Partition Result Files351 HYPERLINK l _bookmark534 Checking the Target Specification (TSS)351 HYPERLINK l _bookmark536 Methodology for Analyzing Partitioning at Different Stages353 HYPERLINK l _bookmark549 Checking Partitioning Reports360 HYPERLINK l _bookmark554 Parsing Partitioning Reports363
37、 HYPERLINK l _bookmark556 Using Time Domain Multiplexing (TDM)365 HYPERLINK l _bookmark558 Setting General Controls for TDM366 HYPERLINK l _bookmark567 Using HSTDM and HSTDM ERD369 HYPERLINK l _bookmark568 Working with HSTDM Training Methods370 HYPERLINK l _bookmark569 Using proto_rt for HSTDM Train
38、ing370 HYPERLINK l _bookmark574 Using HAPS-Controlled HSTDM Training373 HYPERLINK l _bookmark579 Using the Reset Hijack Method for HSTDM Training375 HYPERLINK l _bookmark585 Estimating System Frequency Based on HSTDM Delays377 HYPERLINK l _bookmark602 Analyzing HSTDM Results388 HYPERLINK l _bookmark
39、603 Using HSTDM Top I/O Flow390 HYPERLINK l _bookmark604 Using Asynchronous Pin Multiplexing (ACPM)393 HYPERLINK l _bookmark605 Using Multi-Gigabyte Transceivers for TDM394 HYPERLINK l _bookmark608 Using Hierarchical Partitioning399 HYPERLINK l _bookmark611 Running Hierarchical Partitioning in Autom
40、atic Single-Pass Mode401 HYPERLINK l _bookmark613 Running Top-Down Hierarchical Partitioning in Manual Mode402 HYPERLINK l _bookmark615 Running System Route for the Top Level405 HYPERLINK l _bookmark617 Congestion Reduction Using Pin Table Assignment407 HYPERLINK l _bookmark618 Generating FPGAs409 H
41、YPERLINK l _bookmark621 Using system_generate to Generate FPGAs409 HYPERLINK l _bookmark622 Analyzing Results after System Generate411 HYPERLINK l _bookmark627 Interactive Partitioning Flow414 HYPERLINK l _bookmark630 Working with Inferred Clocks Driving Inter-FPGA Paths417 HYPERLINK l _bookmark632
42、Implementing Individual FPGAs419 HYPERLINK l _bookmark634 Running Synthesis for Individual FPGAs419 HYPERLINK l _bookmark643 Customizing Scripts to Synthesize, Place, and Route FPGAs423 HYPERLINK l _bookmark654 Updating the Top Level with FPGA Implementation Results428 HYPERLINK l _bookmark658 Using
43、 Multi-Design Mode (MDM)430 HYPERLINK l _bookmark664 Running Designs in Multi-Design Mode: HAPS-100430 HYPERLINK l _bookmark668 Running MDM in a Mixed-Design Setup: HAPS-100 and HAPS-80435 HYPERLINK l _bookmark670 Running MDM in a Mixed-Design Setup: HAPS-80 and HAPS-70436 HYPERLINK l _bookmark672 M
44、DM Planning Guidelines for HAPS-70 and HAPS-80439 HYPERLINK l _bookmark681 Instantiating CAPIM_UI445 HYPERLINK l _bookmark684 Using UMRBus 3.0 with HAPS-100 Modules448 HYPERLINK l _bookmark688 Running Designs in Multi-Design Mode: HAPS-80 and HAPS-70451 HYPERLINK l _bookmark690 MDM Planning Guidelin
45、es (HAPS-80 and HAPS-70)454 HYPERLINK l _bookmark694 Instantiating CAPIM_UI460 HYPERLINK l _bookmark697 Chapter 5: Running the Implementation Flow HYPERLINK l _bookmark699 The Basic Implementation Flow466 HYPERLINK l _bookmark702 Running Pre-Map468 HYPERLINK l _bookmark717 Mapping to Hardware475 HYP
46、ERLINK l _bookmark738 Mapping the Design484 HYPERLINK l _bookmark741 Synthesizing Based on Design Intent488 HYPERLINK l _bookmark757 Using Distributed Processing492 HYPERLINK l _bookmark765 Setting Options to Run Distributed Processing493 HYPERLINK l _bookmark768 Using CDPL for Distributed Processin
47、g495 HYPERLINK l _bookmark773 Running Distributed Compile498 HYPERLINK l _bookmark782 Running Distributed Synthesis501 HYPERLINK l _bookmark790 Analyzing Results506 HYPERLINK l _bookmark792 Checking Reports and Log Files506 HYPERLINK l _bookmark804 Viewing Results in a Schematic511 HYPERLINK l _book
48、mark807 Exploring a Schematic with find and expand514 HYPERLINK l _bookmark808 Querying Incremental Results515 HYPERLINK l _bookmark817 Querying Jobs517 HYPERLINK l _bookmark819 Querying Metrics for a Design519 HYPERLINK l _bookmark821 Dealing with Black Boxes in the Synthesized Netlist521 HYPERLINK
49、 l _bookmark828 Checking Timing Results523 HYPERLINK l _bookmark829 Generating and Viewing Timing Reports523 HYPERLINK l _bookmark841 Viewing and Correlating Results with the Timing Report View531 HYPERLINK l _bookmark848 Generating Custom Timing Reports with the Timing Analyst536 HYPERLINK l _bookm
50、ark851 Checking Clock Information541 HYPERLINK l _bookmark853 Running System-Level Timing Analysis (SLTA)542 HYPERLINK l _bookmark863 Handling Errors and Warnings545 HYPERLINK l _bookmark864 Working with Errors and Warnings545 HYPERLINK l _bookmark869 Manipulating Message Display and Reporting546 HY
51、PERLINK l _bookmark883 Running Simulation552 HYPERLINK l _bookmark889 Setting up the Tools and Testbench553 HYPERLINK l _bookmark893 Running Gate-Level Simulation for a Single-FPGA Design555 HYPERLINK l _bookmark899 Running RTL Simulation for a Multi-FPGA Design557 HYPERLINK l _bookmark905 Simulatin
52、g Post-Partition Designs562 HYPERLINK l _bookmark921 Running Gate-Level Simulation for a Multi-FPGA Design568 HYPERLINK l _bookmark924 Running DUT/IP Separation Simulation Flow for HAPS-100570 HYPERLINK l _bookmark925 Generating a Testbench from FSDB570 HYPERLINK l _bookmark928 Running Place and Rou
53、te571 HYPERLINK l _bookmark932 Running Place-and-Route Exploration571 HYPERLINK l _bookmark937 Running Place and Route without Exploration575 HYPERLINK l _bookmark945 Customizing Scripts to Run Vivado (Single-FPGA Designs)578 HYPERLINK l _bookmark947 Importing Place and Route Results for Backannotat
54、ion579 HYPERLINK l _bookmark949 Resynthesizing After Place and Route581 HYPERLINK l _bookmark951 Analyzing Congestion Issues584 HYPERLINK l _bookmark953 Using Congestion-Reducing Techniques584 HYPERLINK l _bookmark957 Troubleshooting Congestion at Different Design Phases586 HYPERLINK l _bookmark963
55、Using TDM to Reduce SLL Congestion in Vivado593 HYPERLINK l _bookmark964 Working with Mixed-System Designs596 HYPERLINK l _bookmark969 Running in Batch Mode598 HYPERLINK l _bookmark970 Running Batch Mode with a Tcl Script598 HYPERLINK l _bookmark974 Queuing Licenses599 HYPERLINK l _bookmark983 Relea
56、sing the Tool License During Place and Route602 HYPERLINK l _bookmark985 Working with Tcl Scripts and Commands603 HYPERLINK l _bookmark988 Using Tcl Commands and Scripts603 HYPERLINK l _bookmark992 Generating a Tcl Script from the GUI604 HYPERLINK l _bookmark993 Creating a Tcl Script605 HYPERLINK l
57、_bookmark995 Setting Number of Parallel Jobs606 HYPERLINK l _bookmark1000 Preparing to Run on the Hardware609 HYPERLINK l _bookmark1002 Exporting Files for Runtime609 HYPERLINK l _bookmark1006 Configuring Bit Files611 HYPERLINK l _bookmark1007 Generating a Confpro Project612 HYPERLINK l _bookmark101
58、3 Ensuring Hardware Bring-up616 HYPERLINK l _bookmark1020 Configuring HAPS Clocks619 HYPERLINK l _bookmark1021 Running HAPS Hardware Diagnostics621 HYPERLINK l _bookmark1022 Running Data Expansion in a Multi-User Setup622 HYPERLINK l _bookmark1024 Chapter 6: Instrumenting and Debugging Designs HYPER
59、LINK l _bookmark1025 Evaluating Debug Methodology Choices628 HYPERLINK l _bookmark1028 The Instrumentor-Debugger Flow632 HYPERLINK l _bookmark1029 Instrumenting the Design for Debug635 HYPERLINK l _bookmark1032 Instrumenting the Design Before Compiling636 HYPERLINK l _bookmark1036 Instrumenting the
60、Design After Compiling642 HYPERLINK l _bookmark1041 Defining IICE Parameters645 HYPERLINK l _bookmark1053 Selecting Buffer Type651 HYPERLINK l _bookmark1059 Specifying IICE Clocks653 HYPERLINK l _bookmark1068 Making Incremental Instrumentation Changes657 HYPERLINK l _bookmark1069 Making Incremental
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