数字逻辑设计及应用教学英文课件：Lec20-chap 8

1、1Digital Logic Design and ApplicationLecture #20Chapter 8Sequential Logic Design PracticesUESTC, Spring 20132Chapter 7 Sequential Logic Design PrinciplesCombinational logic circuitOutputs = f ( current inputs )Sequential logic circuitOutputs = f ( current inputs + entire input history )stored in mem

2、ory elementsLatches and Flip-Flopsfeedback sequential circuitclocked synchronous state machineMealy machineMoore machine虽然组合逻辑电路能够很好地处理像加、减等这样的操作，但是要单独使用组合逻辑电路，使操作按照一定的顺序执行，需要串联起许多组合逻辑电路，而要通过硬件实现这种电路代价是很大的，并且灵活性也很差。为了实现一种有效而且灵活的操作序列，需要构造一种能够存储各种操作之间的信息的电路时序电路。时序电路可以提高器件利用效率。3Chapter 7 Sequential Log

3、ic Design PrinciplesClock signal clock period, clock frequency, clock tick, duty cycleBistable ElementsMetastable CharacteristicLatchesS-R Latch, D LatchFlip-Flops, F/FEdge-Triggered flip-flopMaster/Slave flip-flopD FFT FFJ-K FFS-R FF4State-Machine StructureNextState Logic FStateMemoryOutputLogicGin

4、putsoutputsexcitationcurrent stateclocksignalexcitationequationtransitionequationoutputequation5State-Machine AnalysisDetermine excitation equation for flip-flop control inputsDetermine output equation from the circuit diagramSubstitute the excitation equations into the flip-flop characteristic equa

5、tions to obtain transition equationsUse the transition equations and output equations to construct a transition/output tableName the states and obtain a state/output table(Optional) Draw a state diagramDescribe the circuit function6State-Machine DesignConstruct state/output table ( or state diagram

6、)(optional) State minimizationState assignmentCreate transition/output tableDerive transition equations and output equationsChoose a flip-flop type for the state memoryConstruct excitation equationsDraw a logic circuit diagram7State-Machine DesignState table transition table transition equationState

7、 diagram transition list transition equationExcitation equationState assignmentFF chooseK-map, (),()(),()Chapter 7 Sequential Logic Design PrinciplesSeveral important conceptionsBi-stable / LatchMeta-stableenable Synchronous/ AsynchronousFinite stateLogic function89Chapter 8Sequential Logic Design P

8、racticesSSI Latches and Flip-FlopsMSI Device: Counters, Shift RegistersOthers: Documents, Iterative, Failure and Metastability108.1 Sequential-Circuit Documentation StandardsGeneral Requirements ( P680 )Logic SymbolsEdge-Triggered indicator, Master/Slave Output indicatorasynchronous preset (at the T

9、op) and clear (at the bottom) all inputs on the left, all outputs on the rightState-Machine Descriptionword descriptions, state tables, state diagrams, transition listsTiming Diagrams and Specifications ( P682 )11CLOCKflip-flop outputscombinationaloutputsflip-flop inputssetup-time marginhold-time ma

10、rgin理论上，时序电路的速度越快越好，但实际应用中，不是越快越好。建立时间限制了时钟的最高频率；保持时间限制了组合电路的最快传输速度。128.2 Latches and Flip-Flops1. SSI Latches and Flip-Flops132. Switch Debouncing+5VSW_LDSWPushSW_LDSW Pushfirst contactbounceSW_LDSWIdeal Case14SW_LSW0011SW_LSW0011Push0011SW_LSW0011SW_LSW110015SW_LSWDSW说明： 开关悬空后， SW_L会稍大于0电平 可在输出端加一

11、级缓冲解决 QQLS QR Q+5V 开关切换时会出现瞬时短路现象，不应与高速 CMOS器件一起使用 可采用锁存器结构。163. Bus Holder CircuitABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATA174. Multibit Registers and Latches4-bit register74x1751D2D3D4DCLKCLR_L1Q1Q_L2Q2Q_L3Q3Q_L4Q4Q_L188-bit (octal)register74x374 ( 3-state output ) OEou

12、tput enable 1974x377clock enable74x273asynchronous clear74x374output enableother octal registers2074x377（Clock enable）ENEN2-input Multiplexer21Register vs. Latch, whats the difference? register: edge-triggered behavior latch: output follows input when C is asserted Octal LatchOctalregister228.4 Coun

13、tersModulus: the number of states in the cycleA modulo-m counter, or a divide-by-m counterAn n-bit binary counterAny sequential circuit whose state diagram is a single cycle.S1S2S3SmS5S4ENENENENENENENENENENENENEN8.4 Counter a modulo-2 counter 23State assignment: S0: 0 S1: 1S0S1 1-bit counterTransiti

14、on table S S* Z 0 1 0 1 0 101Q0Transition equation: Q0*=Q0Q0* Toggle, T F.FCLKOne T F.F for one bit counter,N-bit counter? use N F.F241. Ripple Counters0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 1 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1asynchronous countercounter adderQ3

15、 Q2 Q1 Q0 Toggle Toggle at Q0 Toggle at Q1 Toggle at Q2 In the worst case, the propagation delay of the MSB is ntTQ .252. Synchronous Counters1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。 Using T flip-flop with enable: Q* = ENQ + ENQ = EN QENi = Qi-1Qi-2

16、Q1Q0EN0 =1Q* = D= EN Q Di = (Qi-1 Q1 Q0) Qi D QEN CLK Q Using D flip-flop with enable D0 = 1 Q0 = Q0EN Q T Q26synchronous 4-bit binary up counter1如何加入使能端？ LSB MSB 27synchronous counter with serial enable logicCNTENSerial enable logic28synchronous counter with parallel enable logicCNTEN Parallelenabl

17、e logic 293. A 4-Bit Binary Counter 74x16374x163 Function Table 01111CLKfunction clear load holdhold & RCO=0 count CLR_LLD_LENP ENT0111 0 1 0 1 1It uses D flip-flops internally to facilitate the load and clear functions.With synchronous clear and load inputsP714 Figure 8-28 internal logic diagram fo

18、r the 74x16330CLKENclear and loadQ0Q1Q2Q3D0D1D2D3(Qi-1 Q0) Qi counting32synchronous clear inputLD_LCLR_LCLKQAAcounting functionQi* = (Qi-1 Q1 Q0) Q00000033synchronous load inputLD_LCLR_LCLKQAAcounting functionQi* = (Qi-1 Q1 Q0) Q01102-to-1 MUX34ENP and ENT enable inputsENP ENT ENRCOclear “ripple carry out” signalripple carry outRCO=ENT QD QC QB QA35operate in a free-running modeFree-running 16Count if ENP andENT both asserted.Load if LD is asserted(overrides counting).Clear if CLR is asserted(o