集成电路设计preface

1、EDA-EIS-Wuhan University1集成电路设计 Intigrated Circuit Design第一章第一章 集成电路设计概论集成电路设计概论EDA-EIS-Wuhan University2n李德识nTEL：68774465,nResearch InterestsqIntelligent System / Embedded SystemqSoC Design & VerificationqAd hoc Networks，Wireless Sensor Networks，Mesh NetworksqSignal Detecting & Processing联络

2、方式EDA-EIS-Wuhan University3参考书n数字集成电路数字集成电路设计透视（第二版）设计透视（第二版）Jan MJan M RabaeyRabaey，20042004，清华，清华nDigital Integrated Circuit(A Design Perspective)Digital Integrated Circuit(A Design Perspective)n数字集成电路数字集成电路电路、系统与设计（第二版）电路、系统与设计（第二版） ，RabaeyRabaey，20042004，电子工业。电子工业。n超大规模集成电路与系统导论，John P. Uyemura，

3、2004，电子工业。n现代VLSI电路设计（第二版）（英文），Wolf，2002，科学出版社。n数字集成电路设计（英文影印版），Ken Martin ，电子工业。n专用集成电路Smith，2005，电子工业。nCMOS数字集成电路分析与设计（第三版），Sung-Mo Kang ，电子工业。EDA-EIS-Wuhan University4关于Steve JobsnApple founder /CEOn关键词：iPhone, iPad,ipod,ibook,iMac,Mac OSn领域Pioneer：qPlate Computer Apple，NxETqIntelligent Cell Phon

4、eqDigital Music-iTunesqE-BusinessApp StoreqDigital animated film-Pixar Animation Studio ，Walt DisneyqDigital Textbookn特征：q创新（设计）、追求完美、控制与坚持能力、良好的商业模式创新（设计）、追求完美、控制与坚持能力、良好的商业模式创新距离并不遥远，创新造就神奇。创新距离并不遥远，创新造就神奇。EDA-EIS-Wuhan University5ICs key AdvantagesWhy IC? nSizenSpeednPower ConsumptionnIC to Syste

5、mqSmaller physical sizeqLower power consumptionqReduced costqStable qProtection of Intelligent Property (IP)InnovationEDA-EIS-Wuhan University6课程背景n产业发展产业发展q七个IC产业化基地q北京、上海、深圳、西安、杭州、无锡、成都n社会需求社会需求q人才短缺成为瓶颈，建立人才培养基地；n国家扶持国家扶持q软件及集成电路产业；n产业分工的新特点产业分工的新特点 q知识面要求qFabless (fabrication)，Chipless，Design ho

6、usen知识产权保护该领域知识和能力带来的好处n从传统电子电路到现代技术从传统电子电路到现代技术n电子、信息通信、计算机知识融汇电子、信息通信、计算机知识融汇n源头创新源头创新n高质量就业高质量就业n未来创业基础未来创业基础EDA-EIS-Wuhan University7EDA-EIS-Wuhan University8实验室建设&科学研究n实验室建设qEDA/FPGAqDSPq嵌入式系统n科学研究qSOCn设计与验证方法nCo-Designq互连线qIP CoreqAsicqReconfigurable System,FPGAEDA-EIS-Wuhan University9课程内

7、容n集成电路设计概论集成电路设计概论q集成电路的发展， 设计的要求，设计方法学，设计层次，设计流程。q6hnCMOS集成电路制造技术集成电路制造技术Fabricq半导体材料，集成电路制造技术，CMOS集成电路制造过程。q3hnVerilogHDL建模与仿真建模与仿真-modelingq12hn器件设计技术器件设计技术-DeviceqMOS晶体管的工作原理，MOS晶体管的直流特性， CMOS反相器直流特性。q6hn电路参数及性能电路参数及性能-CircuitqMOS晶体管的参数，信号传输延迟， CMOS电路功耗。q3hn逻辑设计技术逻辑设计技术Logic designqMOS管的串、并联特性，逻

8、辑门的延迟，传输门，CMOS逻辑结构，时钟策略。q6hEDA-EIS-Wuhan University10课程内容（续）n子系统设计子系统设计-Subsystemq加法器，寄存器，流水线，存储器，控制与I/O电路。q12hn版图设计技术版图设计技术-Layoutq版图设计过程，版图设计规则。q3hn系统设计方法与实现技术系统设计方法与实现技术System Designq系统设计方法，系统实现技术，门阵列、宏单元阵列及门海，标准单元实现方式，现场可编程门阵列。q3hn可编程逻辑器件设计技术可编程逻辑器件设计技术Programmable Logic DeviceqFPGA/PLD结构和原理， FP

9、GA/PLD器件编程，FPGA/PLD设计方法与流程，综合设计实例。q12hnSoC设计设计System On Chipq设计经济学，SOC设计方法，验证方法。q3hEDA-EIS-Wuhan University11课程名称及关系q数字逻辑；q电子电路设计；q逻辑设计与数字系统；q计算机辅助VLSI设计；q微电子学概论；qFPGAqEDAEDA-EIS-Wuhan University12课程目标n了解设计流程；了解设计流程；n掌握基本概念；掌握基本概念；n理解并掌握集成电路设计基础知识；理解并掌握集成电路设计基础知识；n设计数字电路并进行优化；设计数字电路并进行优化；n配合配合EDA实验，

10、能够进行前端设计；实验，能够进行前端设计；n具备一定的系统设计能力。具备一定的系统设计能力。EDA-EIS-Wuhan University13学习方法n课堂q侧重理解侧重理解q做好笔记做好笔记n课后q阅读阅读,阅读，阅读阅读，阅读q查阅参考书q认真完成作业认真完成作业-阅读阅读paper，Project，习题，习题n配合qEDA实验q相关HDL设计资料q相关IC设计案例EDA-EIS-Wuhan University14成绩考核n平时成绩：大于30%q作业n任何抄袭行为导致平时成绩为0；n英文表述导致阅读困难，成绩会低于70%；n过度引用，成绩会低于70%。q课堂：登记+课堂作业n考试成绩：

11、小于70%EDA-EIS-Wuhan University15EDA实验使用的环境及工具n环境环境qSUN Solaris，UNIX，LINUXn设计（设计（RTL Design）q文本编辑器qWriting Verifiable, Synthesizable VHDL or Verilogn仿真（仿真（Simulation) qVCSqTestbench ，stimulus generation, assertions, output checkingn逻辑综合（逻辑综合（Synthesis）q综合，优化n静态时序检查（静态时序检查（Timing Analysis）qPMn形式化验证（形式化

12、验证（Formal Verification) qFormalitynFPGAqQuartusIIq实验系统 n电路模拟电路模拟SPICEEDA-EIS-Wuhan University161-1 集成电路发展EDA-EIS-Wuhan University17信息传输的变迁EDA-EIS-Wuhan University18The First ComputernCharles Babbage的世界第一台自动计算器部件差动引擎（Difference Engine，1834)；n25，000 parts；nCost 17,470 Pounds；n基本运算，存放/执行，流水线；n元件继电器(Rel

13、ay)。EDA-EIS-Wuhan University19IBM First Automatic Calculator(Harvard University)EDA-EIS-Wuhan University20ENIAC - The first electronic computer (1946，用于大炮发射表计算)n宾夕法尼亚大学；n18，000个真空管；n30m*1m*3m,30T,174KW;nElectronic ；nUNIVACI第一台商用计算机。EDA-EIS-Wuhan University21The Transistor RevolutionFirst transistorB

14、ell Labs, 1947EDA-EIS-Wuhan University22Transistor RevolutionnTransistor Bardeen (Bell Labs) in 1947；q1965,1972诺贝尔物理奖nBipolar transistor Schockley in 1949；nFirst bipolar digital logic gate Harris in 1956；nFirst monolithic IC Jack Kilby（Texas) in 1959；nFirst commercial IC logic gates (TTL) Fairchild

15、1960；nTTL 1962 into the 1990snECL 1974 into the 1980sEDA-EIS-Wuhan University23The First Integrated Circuits Bipolar logic1960sECL 3-input GateMotorola 1966EDA-EIS-Wuhan University24TransistorsnBipolar (PNP, NPN)nFET (Field-Effect)qJFET (Junction)qMOS (Metal-Oxidation Semiconductor)nNMOSnPMOSnCMOSED

16、A-EIS-Wuhan University25MOSFET TechnologynMOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935nCMOS 1960s, but plagued with manufacturing problemsnPMOS in 1960s (calculators)nNMOS in 1970s (4004, 8080) for speednCMOS in 1980s preferred MOSFET technology because of power benefit

17、snBiCMOS, 坤化镓（Gallium-Arsenide）, 锗硅（Silicon-Germanium）nCMOS工艺EDA-EIS-Wuhan University261-2 摩尔定律（Moores Law）l1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lsemiconductor technology will double its effectiveness every 18 months.16151413121110987654321

18、019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.EDA-EIS-Wuhan University27Transistor Counts1,000,000100,00010,0001,000101001197519801985 19901995 20002005 2010808680286i386i486PentiumPentium ProKP

19、entium IIPentium IIIEDA-EIS-Wuhan University28Moores law in Microprocessors40048008808080858086286386486Pentium procP60.0010.010.1110100100019701980199020002010YearTransistors (MT)2X growth in 1.96 years!Transistors on Lead Microprocessors double every 2 yearsCourtesy, IntelEDA-EIS-Wuhan University2

20、9DRAM Chip Capacity1.6-2.4 m1.0-1.2 m0.7-0.8 m0.5-0.6 m0.35-0.4 m0.18-0.25 m0.13 m0.1 m0.07 mhuman memoryhuman DNAencyclopedia2 hrs CD audio30 sec HDTVbookpage4X growth every 3 years!EDA-EIS-Wuhan University30 Intel 4004 Micro-Processor19712300 transistors1 MHz operation版图LayoutEDA-EIS-Wuhan Univers

21、ity31Intel Pentium (IV) microprocessor2001； 42 Million；2 GHz clock；电压更低，功耗更高；模块化设计；借助自动化设计工具。16 Million transistors (Ultra Sparc III)140 Million transistor (HP PA-8500)EDA-EIS-Wuhan University32芯片尺寸/面积（Die Size）40048008808080858086286386486Pentium procP611010019701980199020002010YearDie size (mm2)7%

22、 growth per year2X growth in 10 yearsCourtesy, IntelEDA-EIS-Wuhan University33FrequencyP6Pentium proc486386286808680858080800840040.111010010001000019701980199020002010YearFrequency (Mhz)Lead Microprocessors frequency doubles every 2 yearsDoubles every2 yearsCourtesy, IntelEDA-EIS-Wuhan University34

23、Power will be a major problem5KW 18KW 1.5KW 500W 40048008808080858086286386486Pentium proc0.1110100100010000100000197119741978 198519922000 20042008YearPower (Watts)Courtesy, IntelLead Microprocessors power continues to increaseEDA-EIS-Wuhan University35Power density40048008808080858086286386486Pent

24、ium procP611010010001000019701980199020002010YearPower Density (W/cm2)Hot PlateNuclearReactorRocketNozzlePower density too high to keep junctions at low tempCourtesy, IntelEDA-EIS-Wuhan University36EDA-EIS-Wuhan University37n速度、面积、功耗是IC设计主要约束条件（多优化目标）。EDA-EIS-Wuhan University38Technology Directions:

25、 SIA（美国半导体协会） RoadmapYear199920022005200820112014Feature size (nm)180130100705035Mtrans/cm2714-2647115284701Chip size (mm2)170170-214235269308354Signal pins/chip76810241024128014081472Clock rate (MHz)6008001100140018002200Wiring levels6-77-88-999-1010Power supply (V)1.81.51.20.90.60.6High-perf power

26、 (W)90130160170174183EDA-EIS-Wuhan University39Source McClean report 2009 BrochureEDA-EIS-Wuhan University40Source: McClean report 2009 BrochureEDA-EIS-Wuhan University41Source: McClean report 2009 BrochureEDA-EIS-Wuhan University42Cell PhoneDigital Cellular MarketAnalog BasebandDigital Baseband(DSP

27、 + MCU)PowerManagementSmall Signal RFPowerRF20102010年中国手机产量增长年中国手机产量增长31%31%，达，达10.1510.15亿部，亿部，占全球的占全球的 71%,71%,手机出口手机出口7.587.58亿部亿部 EDA-EIS-Wuhan University43SoC Example: Network ChipEDA-EIS-Wuhan University441-3 IC 分类n按规模分类：qSSI，少于100门；qMSI，100-1000门；qLSI，1000-10，000门；qVLSI （Very-Large-Scale-Inte

28、grated-Circuits) ，10万-100万门；qULSI（Ultra-Large-Scale-Integrated-Circuits)，1000万门以上。EDA-EIS-Wuhan University45按工艺分类n微米，特征尺寸大于1微米；n亚微米，小于1微米；n深亚微米deep submicron (DSM) ，小于0.6微米；n超深亚微米，小于0.1微米；n典型工艺：q5um, 3um, 2um, 1.2umq1.0um, 0.8um, 0.6um/0.5um, 0.35umq0.25um, q0.07um, . 0.01umEDA-EIS-Wuhan University4

29、6按实现方式分类n全定制ICq积木式基于单元的设计，基于IP复用的设计（SOC）。q任意方式。n半定制IC（未制造，根据功能设计改变内部连线）q门阵列q标准单元n可编程IC（已封装，可改变引脚及功能）qPLD，CPLDqFPGAEDA-EIS-Wuhan University47按用途分类n通用ICq标准部件，如：译码器、多路选通器；q作为商品的存储器、微处理器。n专用ICqASIC（Application specification Integrated Circuits)q如:卫星芯片、GPS芯片、玩具芯片等。EDA-EIS-Wuhan University481-4 产业（Semicon

30、ductor Related Industry）nDesign (Fabless Company) nCAD Software (EDA) Synopsys, Cadence, MentornManufacturing nMaterial (Wafer, Chemical) nPackaging nTesting Single dieWaferEDA-EIS-Wuhan University49芯片代工厂（chip foundry industry)n台积电（TSMC），台湾，58.6亿美元（2003）；n联电（UMC），台湾，27.4亿美元；n特许半导体（Chartered)，新加坡，7.2

31、5亿美元；nIBM，5.55亿美元；nNEC，4.25亿美元；n中芯国际（SMIC），中国，3.65亿美元；n现代，韩国，3.4亿美元；IC Insight,2004EDA-EIS-Wuhan University502009 Top20 EDA-EIS-Wuhan University51EDA-EIS-Wuhan University521-5 设计挑战（Design Challenges）n微观问题q速度ultra-high speedsq功耗power dissipation and supply rail dropq互连线延迟interconnectq噪声、串扰noise, cros

32、stalkq可靠性reliabilityq时钟分布clock distributionn宏观问题q上市时间time-to-marketq设计复杂性design complexity (millions of gates)q抽象层次high levels of abstractionsq设计重用reuse and IPq片上系统systems on a chip (SoC)q协同设计Co-designEDA-EIS-Wuhan University531-6 层次化设计EDA-EIS-Wuhan University54设计鸿沟1101001,00010,000100,0001,000,0001

33、0,000,000200319811983198519871989199119931995199719992001200520072009101001,00010,000100,0001,000,00010,000,000100,000,000Logic Tr./ChipTr./Staff Month.xxxxxxx21%/Yr. compoundProductivity growth ratex58%/Yr. compoundedComplexity growth rate10,0001,0001001010.10.010.001Logic Transistor per Chip(M)0.0

34、10.11101001,00010,000100,000Productivity(K) Trans./Staff - Mo.Source: SematechComplexity outpaces design productivityComplexityCourtesy, ITRS RoadmapEDA-EIS-Wuhan University55层次化设计-动因q工艺特征参数按 0.7/generation递减；q芯片功能倍增2x/generation；q功能费用按 2x/generation递减；q芯片价格无显著增加；q如何设计更多functions?q设计工程师数量不随摩尔定律倍增（2年

35、）-n需要更有效的设计方法q使用不同的抽象层次。EDA-EIS-Wuhan University56抽象抽象(Abstraction)EDA-EIS-Wuhan University57设计抽象层次（Design Abstraction Levels）Major levels of abstractionq设计描述( 功能、性能） specification;q结构设计（模块） architecture;q逻辑设计（门、寄存器） logic design;q电路设计（晶体管，尺寸满足速度速度、功率需要） circuit design;q版图设计（寄生参数） layout.SYSTEMLOGIC

36、CIRCUITVoutVinCIRCUITVoutVinMODULE+DEVICEn+SDn+GEDA-EIS-Wuhan University58问题n每个层次满足同样的设计要求/约束；n不同层次具有一致性/等价性；n如何评估设计性能 (gate, block, )?qCost（面积）qReliabilityqSpeed (delay, operating frequency) qPower dissipationEDA-EIS-Wuhan University59Dealing with complexitynVLSI设计漏斗$ ￥IdeaSand (silicon)CADEngineer

37、MarketSuper ICVLSI设计漏斗设计漏斗EDA-EIS-Wuhan University60设计方法nDivide-and-conquer自顶向下（top-down)的设计方法nGroup several components into larger components 自低向上(bottom-up)的设计方法qtransistors gates;qgates functional units;qfunctional units processing elements;qetc.EDA-EIS-Wuhan University61例：Component Hierarchytopi

38、1xxxi2EDA-EIS-Wuhan University62A hierarchical logic designzbox1box2xEDA-EIS-Wuhan University63例:Refinements of electronic design EDA-EIS-Wuhan University64Design abstractionsspecificationbehaviorregister-transferlogiccircuitlayout自然语言ExecutableprogramSequentialmachinesLogic gatestransistorsrectangl

39、esThroughput,design timeFunction units,clock cyclesLiterals, logic depthnanosecondsmicronsTop-downBottom-upEDA-EIS-Wuhan University65例： Layout and its abstractionsnLayout for dynamic latch:EDA-EIS-Wuhan University66棍棒图Stick diagramEDA-EIS-Wuhan University67Transistor schematicEDA-EIS-Wuhan Universit

40、y68Mixed schematicinverterTransfer gateEDA-EIS-Wuhan University69Circuit abstractionn晶体管尺寸对速度、功耗的影响q表达方式Continuous voltages and time:EDA-EIS-Wuhan University70Digital abstractionn逻辑电平、离散时间discrete time、延迟时间、驱动能力n布尔方程EDA-EIS-Wuhan University71寄存器传输器级（Register-Transfer-Level）抽象n例：Register_X A+Bq只描述系统如

41、何操作，不考虑具体部件(电路）n抽象元件components：运算、存储n数据类型data typesn时钟周期为单位n状态机、数据流图DFG、控制数据流图CDFG+0010000101000111EDA-EIS-Wuhan University721-7 设计流程n设计（ Design ）Authoringn版图（ Layout ） Formattingn制造（ Fabrication ） Printingn封装（ Packaging ） Bindingn测试（ Testing ）CheckingEDA-EIS-Wuhan University73Design ProcessEDA-EIS-

42、Wuhan University74Typical Design Flow - Industryn产品需求product requirementsn设计描述design specificationn设计建模（model/RTL/HDL）n仿真simulation modelqBehavior and/or RTLn功能验证verificationn逻辑综合Synthesize to gate level modeln优化Logic minimization/ 面向测试的设计Design for Testn布局布线Place and route/ Physical analysisn制造Fabr

43、icationn测试TestingEDA-EIS-Wuhan University75How to Design an ASICRTLGateTape outMASKFUNCTIONAL SIMULATIONSYNTHESISSTATIC TIMING ANALYSISFLOORPLAN, PLACE/ROUTEPHYSICAL VERIFICATIONTIMING VERIFICATIONVHDLVerilogVITALVerilogGDSIIspecificationDESIGN PLANNINGLogical designLogic Verification“CAE”Fabricatio

44、nPackagingTestingSystem Designentry accumulator is port (DI : in integerDO : inout integer := 0CLK : in bit) ;end accumulator;Physical designPhysical Verification“IC CAD”VITAL（VHDL Initiative Toward ASIC Library） EDA-EIS-Wuhan University76HDL-based Design Flown建立行为模型Create behaviorn测试平台Consider test

45、abilityn功能仿真Verify/simulate functionalityn综合Synthesize gate-level Netlistn等效性检查Compare gate-level and behaviorn静态时序分析Verify timingn布局布线Place & routen设计规则检查Verify design rulesn参数抽取Extract parasiticsEDA-EIS-Wuhan University77设计说明1.Chip Overview2.Feature List3.Block Diagram4.Function SpecificationE

46、DA-EIS-Wuhan University78设计规划Design Planningn划分为可综合模块； n编写RTL 代码；n估计延迟时间。ChipChipSynthesizedCoreMemoryRandom LogicHardCoreAnalogRandom LogicDatapathRFEDA-EIS-Wuhan University79综合 （Synthesis）n为特定功能，从一个想法（为特定功能，从一个想法（idea）到可制造器件）到可制造器件（manufacturable device）的转换（）的转换（transformation）过程。过程。n自高层次描述到下一层次描述

47、的转换过程。自高层次描述到下一层次描述的转换过程。n系统级综合系统级综合算法综合算法综合逻辑综合逻辑综合物理综合物理综合nSynthesis =Translation + Optimization + mappingnRTL Description in VHDL or Verilog HDLEDA-EIS-Wuhan University80Logic Synthesisarchitecture VHDL_1 of VHDL isbegin process begin if CLOCKevent and CLOCK = 1 then if ENABLE = 1 then TOGGLE = not TOGGLE; end if; end if; end process;end VHDL_1;Gate-level Netlist:inv1a U1 (wire3, wire5);dff1 U2 (wire1, wire2, clk);EDA-EIS-Wuhan University81Estimated TimingPlaced ComponentPlaced ComponentNetlist EstimatePhysical EstimateEDA-EIS-Wuhan