处理器设计全部代码

1、代码一顶层模块module MIPS_C(clk,rst,MIPS_out ); input clk,rst; output 7:0MIPS_out; wire 31:0ALU_DC;wire 31:0Pc_out;wire 5:0op;wire 5:0func;wire ALUSrcA;wire ALUSrcB;/wire Load_Mem;wire MemtoReg;wire RegDst;wire ExtOp;/wire MemWr;wire RegWr;wire 31:0instruct; wire PcWrite;wire 31:0imm32;wire 15:0imm16;wire

2、25:0target;wire 31:0rdata2;wire 31:0rdata1;wire 31:0rdata3;wire ALU_CLK;wire 31:0Mem_Dout;wire 4:0rt;wire 4:0rd;wire 4:0rs;wire 31:0ALU_DB;wire 31:0ALU_DA;wire 31:0wdata;wire 4:0waddr;wire Branch;wire Jump;wire 31:0Mem_Din;wire ALU_OverFlow;wire ALU_ZERO;wire 4:0shamt;wire 4:0ALU_SHIFT;assign MIPS_o

3、ut=rdata37:0;Main_control main_control( .rst(rst), .op(op), .ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.MemtoReg(MemtoReg),.RegDst(RegDst),.ExtOp(ExtOp), .PcWrite(PcWrite),.RegWr(RegWr),.clk(clk) ); Fetch_top fetch_top(.clk(clk), .rst(rst), .instruct(instruct), .ALU_DA(ALU_DA), .Jump(Jump), .Branch(Branch)

4、, .PcWrite(PcWrite), .ALU_DB(ALU_DB), .Pc_out(Pc_out) ); decode Decode(.instruct(instruct), .op(op), .rs(rs), .rt(rt), .rd(rd), .func(func), .shamt(shamt), .imm16(imm16), .target(target) );regfile Regfile (.clk(clk), .rst(rst), .RegWr(RegWr), .waddr(waddr), .wdata(wdata), .raddr1(rs), .rdata1(rdata1

5、), .raddr2(rt), .rdata2(rdata2) , .rdata3(rdata3) ); /*Memory mem ( .Mem_Adr(Mem_Adr), .MemWr(MemWr), .rst(rst), .clk(clk), .Mem_Din(rdata2), .Mem_Dout(Mem_Dout) );*/ Imm imm( .rst(rst), .imm16(imm16),.ExtOp(ExtOp),.imm32(imm32);flag Flag(.ALU_DA(ALU_DA), .ALU_DB(ALU_DB), .op(op), .func(func), .Jump

6、(Jump), .Branch(Branch) ); ALU_top alu_top ( .ALU_CLK(clk),.rst(rst),.func(func),.op(op),.ALU_DA(ALU_DA),.ALU_DB(ALU_DB),.ALU_SHIFT(shamt),.ALU_ZERO(ALU_ZERO),.ALU_OverFlow(ALU_OverFlow),.ALU_DC(ALU_DC) );data_select DATA_select(.ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.MemtoReg(MemtoReg),.RegDst(RegDst)

7、,.imm32(imm32),.target(target),.rdata2(rdata2),.rdata1(rdata1),.ALU_DC(ALU_DC),.Mem_Dout(Mem_Dout),.rt(rt),.rd(rd),.ALU_DB(ALU_DB),.ALU_DA(ALU_DA),.wdata(wdata),.waddr(waddr) );endmodule二主控模块module Main_control(clk,rst,op,ALUSrcA,ALUSrcB,MemtoReg,RegDst,ExtOp, PcWrite,RegWr ); input clk,rst; input 5

8、:0op; output reg ALUSrcA; output reg ALUSrcB; output reg MemtoReg; output reg RegDst; output reg ExtOp; output reg RegWr; output reg PcWrite; reg 3:0state; reg 3:0next_state; parameter State_IR = 4b0000,/fetch adder State_decode = 4b0001, /decode State_MemCalc= 4b0010,/store calculate adder State_Me

9、mRD = 4b0011 , /read Mem State_MemRDend= 4b0100 , /read Mem finish State_MemWr = 4b0101 ,/write MEm State_R = 4b0110,/Rzhixing State_Rend = 4b0111,/Rfinish State_B = 4b1000,/Bzhixing State_J = 4b1001;/jzhilingalways(posedge clk or posedge rst) beginif(rst) state = 4b0000;else state =next_state; enda

10、lways(*) begin case(state)4b0000: begin next_state=4b0001;end4b0001: beginnext_state3=(op5)&(op4)&(op3)&op2&(op1)&op0) | (op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state2=(op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state1=(op5)&(op4)&(op3)&(op2)&(op1)&(op0) |(op5)&(op4)&(op3)&(op2)&(op1)&(op0)|(op5)&(op4

11、)&(op3)&(op2)&(op1)&(op0);next_state0=(op5&(op4)&op3&(op2)&(op1)&(op0);end/*4b0010:beginnext_state=4b0011; end*/ 4b0010:beginnext_state3=1b0;next_state2=op5&(op4)&(op3)&(op2)&op1&op0;next_state1=(op5)&(op4)&(op3)&(op2)&(op1)&(op0);next_state0=1b1; end4b0011:beginnext_state=4b0100;end4b0100:beginnext

12、_state=4b0000;end4b0101:begin next_state=4b0000;end4b0110:beginnext_state=4b0111;end4b0111:beginnext_state=4b0000;end4b1000:begin next_state=4b0000;end4b1001:beginnext_state=4b0000;end endcaseendalways(posedge clk)begincase(state)4b0000: beginALUSrcA=0;ALUSrcB=1;/Load_Mem=0;MemtoReg=0;RegDst=0; ExtO

13、p=1; /MemWr=0; RegWr=0; PcWrite=1; end4b0001: beginALUSrcA=0; ALUSrcB=1;/Load_Mem=0;MemtoReg=0;RegDst=0; ExtOp=0; /MemWr=0; RegWr=0; PcWrite=0;end4b0010: beginALUSrcA=0;ALUSrcB=1;/Load_Mem=1;MemtoReg=1;RegDst=0; ExtOp=1; /MemWr=0; RegWr=0; PcWrite=0; end4b0011: beginALUSrcA=0;ALUSrcB=0;/Load_Mem=1;M

14、emtoReg=1;RegDst=0; ExtOp=0; /MemWr=0; RegWr=0; PcWrite=0; end 4b0100: beginALUSrcA=0;ALUSrcB=0;/Load_Mem=0;MemtoReg=0;RegDst=0; ExtOp=0; /MemWr=0; RegWr=1; PcWrite=0; end4b0101:beginALUSrcA=0;ALUSrcB=1;/Load_Mem=1;MemtoReg=0;RegDst=0; ExtOp=0; /MemWr=1; RegWr=1; PcWrite=0;end 4b0110: beginALUSrcA=0

15、;ALUSrcB=0;/Load_Mem=0;MemtoReg=0;RegDst=1; ExtOp=0; /MemWr=0; RegWr=0; PcWrite=0; end4b0111: beginALUSrcA=0;ALUSrcB=0;/Load_Mem=0;MemtoReg=1;RegDst=1; ExtOp=0; /MemWr=0; RegWr=1; PcWrite=0; end4b1000: beginALUSrcA=0;ALUSrcB=1;/Load_Mem=0;MemtoReg=0;RegDst=0; ExtOp=1; /MemWr=0; RegWr=0; PcWrite=1; e

16、nd 4b1001: beginALUSrcA=1;ALUSrcB=0;/Load_Mem=0;MemtoReg=0;RegDst=0; ExtOp=0; /MemWr=0; RegWr=0; PcWrite=0; end endcase endendmodule三取指模块（1）顶层module Fetch_top(clk,rst,instruct,ALU_DA,Jump,Branch,PcWrite,ALU_DB,Pc_out ); input clk,rst; input 31:0ALU_DA; input Jump,Branch,PcWrite; input 31:0ALU_DB; ou

17、tput31:0 instruct; output 31:0Pc_out; fetch FETCH(.Pc_out(Pc_out),.instruct(instruct) );pc PC( .rst(rst),.ALU_DA(ALU_DA),.Jump(Jump),.Branch(Branch),.Pc_out(Pc_out),.ALU_DB(ALU_DB),.PcWrite(PcWrite) );endmodule(2)取指module fetch(Pc_out,instruct );input31:0Pc_out;output 31:0instruct;wire 31:0store0:31

18、; assign store32h00 = 32b000000_00001_00000_00011_00000_100000;/jia assign store32h01 = 32b000000_00001_00000_00011_00000_100000;/jiaassign store32h02 = 32b000000_00111_00110_00111_00000_100010; /减一assign store32h03 = 32b000101_00111_00000_00000_00000_000001;/不等跳转assign store32h04 = 32b000000_00011_

19、00100_00011_00000_100000;/jiaassign store32h05 = 32b000000_01000_00110_00111_00000_100010; /减一assign store32h06 = 32b000101_00111_00000_00000_00000_000001;/不等跳转assign store32h07 = 32b000000_00101_00010_00011_00000_100000;/jiaassign store32h08 = 32b000000_00111_00110_00111_00000_100010; /减一assign sto

20、re32h09 = 32b000101_00111_00000_00000_00000_000001;/不等跳转assign store32hA = 32b000000_00011_00010_00011_00000_100101; / huofeiassign store32h0B = 32b000000_01000_00110_00111_00000_100010; /减一assign store32h0C = 32b000101_00111_00000_00000_00000_000001;/不等跳转assign store32h0D = 32b101000_00000_00000_00

21、000_00000_000000;/ assign instruct = storePc_out;endmodule（3）程序计数器module pc(rst,Jump,Branch,Pc_out,ALU_DA,PcWrite,ALU_DB );input 31:0ALU_DA;input 31:0ALU_DB;input Jump,Branch,rst,PcWrite;output reg 31:0Pc_out;always(posedge PcWrite)beginif(rst)Pc_out=32h00; else if(PcWrite) begin if (Jump) Pc_out=AL

22、U_DA; else if (Branch) Pc_out=Pc_out-ALU_DB;else Pc_out=Pc_out+1; end else Pc_out=Pc_out;end endmodule四译码模块module decode(instruct,op,rs,rt,rd,func,shamt,imm16,target); input 31:0instruct; output reg 5:0op; output reg4:0rs,rt,rd; output reg4:0shamt; output reg5:0func; output reg15:0imm16; output reg

23、25:0target; always(*) begin op5:0=instruct31:26; rs4:0=instruct25:21; rt4:0=instruct20:16; rd4:0=instruct15:11; shamt4:0=instruct10:6; func5:0=instruct5:0; imm1615:0=instruct15:0; target25:0=instruct25:0; end endmodule 五寄存器模块module regfile( inputclk,input rst,input RegWr, input4:0waddr, input31:0wda

24、ta, input4:0raddr1,output31:0 rdata1, input4:0raddr2, output31:0 rdata2,output31:0 rdata3);reg31:0 regs0:8;/Write operationalways (posedge clk or posedge rst) begin if(rst) begin regs0=32b0; regs1=32b00000000_00000000_00000000_00001100; regs2=32b00000000_00000000_00000000_00000000; regs3=32b0; regs4

25、=32b00000000_00000000_00000000_11000000; regs5=32b00000000_00000000_00000000_11100111; /regs6=32b00000000_00000000_00000000_00000010; regs6=32b00000000_01011111_01111000_01000000;/0.5/regs7=32b00000000_00000000_00000000_00000001; regs7=32b00000010_11111010_11110000_10000000;/1 /regs8=32b00000000_000

26、00000_00000000_00000011; regs8=32b00011111_01001010_11011101_01000000;/10.5 end else beginif(RegWr= 1b1) & (waddr != 5h0) begin regswaddr = wdata; end endend/Read port1 operation assign rdata1 = (raddr1 = 5d0) ? 32d0 : regsraddr1;/Read port2 operation assign rdata2 = (raddr2 = 5d0) ? 32d0 : regsradd

27、r2; assign rdata3 = regs3;endmodule 六立即数扩展块module Imm(rst,imm16,ExtOp,imm32); input rst; input ExtOp; input 15:0imm16; output 31:0imm32; reg31:0 bus1; always(*) if(rst) bus1=32b0; else if(imm1615=0) begin bus131:16=16b0000_0000_0000_0000; bus115:0=imm1615:0; end else if(imm1615=1) begin bus131:16=16

28、b1111_1111_1111_1111; bus115:0=imm1615:0; end assign imm32 = (ExtOp=1)?bus1:imm32; endmodule七部分控制信号产生块module flag(ALU_DA,ALU_DB,op,func,Jump,Branch); input 31:0ALU_DB; input 31:0ALU_DA; input 5:0op; input 5:0func; output reg Jump; output reg Branch; always(*) begin if(op=6b101000) Jump=1; else Jump=

29、0; end always(*) case(op) 6b000100: begin if(ALU_DA=ALU_DB) Branch=1; else Branch=0; end 6b000101: begin if(ALU_DA=ALU_DB) Branch=0; else Branch=1; end default Branch=0;endcase endmodule八逻辑运算模块（1）顶层模块module ALU_top(ALU_CLK,rst,func,op,ALU_DA,ALU_DB,ALU_SHIFT,ALU_ZERO,ALU_OverFlow,ALU_DC );input ALU_

30、CLK;input rst;input 5:0func;input5:0op;input 31:0ALU_DA;input 31:0ALU_DB;input 4:0ALU_SHIFT;output ALU_ZERO;output ALU_OverFlow;output 31:0 ALU_DC;wire3:0 ALU_ctr;wire 3:0alu_clt; ALU_control alu_control( .ALU_CLK(ALU_CLK),.rst(rst),.func(func),.op(op),.ALU_ctr(ALU_ctr);ALU alu (.ALU_DA(ALU_DA), .AL

31、U_DB(ALU_DB),.alu_clt(ALU_ctr),.alu_shift(ALU_SHIFT),.ALU_Zero(ALU_ZERO),.Alu_Overflow(ALU_OverFlow),.ALU_Dout(ALU_DC);endmodule(2)运算控制块module ALU_control( ALU_CLK,rst,func,op,ALU_ctr); input rst,ALU_CLK; input 5:0op; input 5:0func; output reg3:0ALU_ctr; reg 3:0ins; always(*) if(op=6b0) case(func) 6

32、b000010:ins3:0=4b0000; 6b100000:ins3:0=4b0001; 6b000111:ins3:0=4b0010; 6b100101:ins3:0=4b0011; 6b000100:ins3:0=4b0100; 6b000001:ins3:0=4b0101; 6b000110:ins3:0=4b0110; 6b001000:ins3:0=4b0111; 6b001001:ins3:0=4b1111; 6b000101:ins3:0=4b1101; 6b001010:ins3:0=4b1110; endcase else case(op) 6b001000:ins3:0

33、=4b0001; 6b001001:ins3:0=4b0000; 6b001100:ins3:0=4b0101; 6b001101:ins3:0=4b0100; 6b100011:ins3:0=4b0001; 6b101011:ins3:0=4b0001; 6b001010:ins3:0=4b0111; 6b001011:ins3:0=4b0110; 6b000100:ins3:0=4b0100; 6b000101:ins3:0=4b0100; endcasealways(posedge ALU_CLK) if(rst) ALU_ctr=4b0; else ALU_ctr3:0=ins3:0;

34、 endmodule (3)运算模块module ALU(ALU_DA,ALU_DB,alu_clt,alu_shift,ALU_Zero,Alu_Overflow,ALU_Dout);input 31:0 ALU_DA;input 31:0 ALU_DB;input 3:0 alu_clt;input 4:0 alu_shift;output ALU_Zero;output Alu_Overflow;output 31:0 ALU_Dout;reg 31:0 ALU_Dout;wire 1:0 OPctr;wire SUBctr;wire ANDctr;wire OVctr;wire SIG

35、ctr;reg 31:0 SLL_M,SRL_M,SRA_M;assign SUBctr = alu_clt2;assign ANDctr = alu_clt0;assign OVctr = !alu_clt1&alu_clt0;assign SIGctr = alu_clt0;assign OPctr1 = alu_clt2&alu_clt1|alu_clt3;assign OPctr0 = alu_clt1;always(*)begin case(alu_shift) 5b00000:SRL_M31:0=ALU_DB31:0; 5b00001:SRL_M31:0=1b0,ALU_DB31:

36、1; 5b00010:SRL_M31:0=2b0,ALU_DB31:2; 5b00011:SRL_M31:0=3b0,ALU_DB31:3; 5b00100:SRL_M31:0=4b0,ALU_DB31:4; 5b00101:SRL_M31:0=5b0,ALU_DB31:5; 5b00110:SRL_M31:0=6b0,ALU_DB31:6; 5b00111:SRL_M31:0=7b0,ALU_DB31:7; 5b01000:SRL_M31:0=8b0,ALU_DB31:8; 5b01001:SRL_M31:0=9b0,ALU_DB31:9; 5b01010:SRL_M31:0=10b0,AL

37、U_DB31:10; 5b01011:SRL_M31:0=11b0,ALU_DB31:11; 5b01100:SRL_M31:0=12b0,ALU_DB31:12; 5b01101:SRL_M31:0=13b0,ALU_DB31:13; 5b01110:SRL_M31:0=14b0,ALU_DB31:14; 5b01111:SRL_M31:0=15b0,ALU_DB31:15; 5b10000:SRL_M31:0=16b0,ALU_DB31:16; 5b10001:SRL_M31:0=17b0,ALU_DB31:17; 5b10010:SRL_M31:0=18b0,ALU_DB31:18; 5

38、b10011:SRL_M31:0=19b0,ALU_DB31:19; 5b10100:SRL_M31:0=20b0,ALU_DB31:20; 5b10101:SRL_M31:0=21b0,ALU_DB31:21; 5b10110:SRL_M31:0=22b0,ALU_DB31:22; 5b10111:SRL_M31:0=23b0,ALU_DB31:23; 5b11000:SRL_M31:0=24b0,ALU_DB31:24; 5b11001:SRL_M31:0=25b0,ALU_DB31:25; 5b11010:SRL_M31:0=26b0,ALU_DB31:26; 5b11011:SRL_M

39、31:0=27b0,ALU_DB31:27; 5b11100:SRL_M31:0=28b0,ALU_DB31:28; 5b11101:SRL_M31:0=29b0,ALU_DB31:29; 5b11110:SRL_M31:0=30b0,ALU_DB31:30; 5b11111:SRL_M31:0=31b0,ALU_DB31; default: SRL_M31:0=ALU_DB31:0; endcaseendalways(*)begin case(alu_shift) 5b00000:SLL_M31:0=ALU_DB31:0; 5b00001:SLL_M31:0=ALU_DB30:0,1b0;

40、5b00010:SLL_M31:0=ALU_DB29:0,2b0; 5b00011:SLL_M31:0=ALU_DB31:3,3b0; 5b00100:SLL_M31:0=ALU_DB31:4,4b0; 5b00101:SLL_M31:0=ALU_DB31:5,5b0; 5b00110:SLL_M31:0=ALU_DB31:6,6b0; 5b00111:SLL_M31:0=ALU_DB31:7,7b0; 5b01000:SLL_M31:0=ALU_DB31:8,8b0; 5b01001:SLL_M31:0=ALU_DB31:9,9b0; 5b01010:SLL_M31:0=ALU_DB31:10,10b0; 5b01011:SLL_M31:0=ALU_DB31:11,11b0; 5b01100:SLL_M31:0=ALU_DB31:12,12b0; 5b01101:SLL_M31:0=ALU_DB31:13,13b0; 5b01110:SLL_M31:0=ALU_DB31:14,14b0; 5b01111:SLL_M31:0=ALU_DB31:15,15b0; 5b10000:SLL_M31:0=ALU_DB31:16,16b0; 5b10001:SLL_M31:0=ALU_DB31:17,17b0; 5b10010: