VHDL课程设计----四路抢答器

1、考试序列号课程设计课程名称FPGA课程设计题目名称兀路抢答器学生学院物理与光电工程学院专业班级电子科学与技术10（ 1）班学号3110008572学生姓名黄灿群联系方导教师罗俊丰2012年12月8日一、设计思想本设计为一个四路抢答器，其中输入输出端是复位信号CLR全局时钟CLK1HZ模块时钟CLK2模块使能端EN四路输入信号A、B C、D,加分健ADD 减分健SUB还有五路输出信号 A1、B1、C1、D1、E1，以及八个数码管 NUMG NUMWQA QB J1、J2、J3、J4分别用于计时，计分，显示抢答者，犯规者。本四路抢答器具有能显示超前抢答台号并显示犯规警报，

2、抢答开始后20s倒计时，20s倒计时后无人抢答显示超时警报。当有一路抢答按键被按下，该路抢答 信号将其余各路抢答信号封锁，同时蜂鸣器响起，直到该路按键松开，显示牌显 示该路抢答台号。主持人可以给犯规和答错者扣分，给答对者加分，预先给每台5 分,以后每次扣1分或者给1分。二、设计框图CLR CLK EN CLK2A B C D EN CLR三、模块介绍1抢答器模块（QDJB）! * PS * 91 IR fl I B B 4-9 BB Ii QDJBCLRSOUNDCLK2A1ENB1AC1BD1CNUMG|3._0DNUMW3.Oinst2抢答为四路分别是A、B、C、D，理论上有16种可能情况

3、，但由于芯片反应速 度快，基本不会出现多路同时响应，所以实际上只有 4种可能情况。当使能端 EN为高电平时方可抢答，有抢答时，SOUND蜂鸣器会响应，同时锁定该时刻 四种状态，并显示抢答者或犯规者。2、计时器（JSQ）.:JSQn:一CLR 广1 KE1QA3.OQB3.OJ.r-ENCLK2a1Sr I instit该计时器具有20秒倒计时，QB是十位，QA是个位，E1为显示时间到，将会出现闪烁，当复位信号为高电平时数码管为 20，使能端EN为高电平时开始倒 计时。CLK2是本模块时钟，用于使E1闪烁。3、计分器（JFQ）计分器中ABCD仍为四路抢答输入信号，ADD , SUB是实现加分减分

4、功能，当 ADD与SUB同为高电平时计分回到初始值 5,当时钟CLK上升沿到来时若A 为高电平且ADD为高电平时，J1的值加1,若A为高电平且SUB为高电平时, J1的值减1;以此类推，J1到J4分别时ABCD的对应计分器。4、总体组合模块（QDQ）cutCUON3 训EMS3 01C112cut3OJN0CU2A1EN01Aci目01uNLMGP .也LJWu *!甲Ml MM rd T-y g阳卩n a -CI 1 :.v F? 四、仿真图1、抢答模块仿真图LrLnTLrLirLmrLimrLrLirLTrLrL-LrLTrLrL-LrLTrLrL-LrLTm-Lmr!|! i|i|! |

5、 |i|!|i|!|i|!|!|!| |!|ULKCLE罪UBCLK21EDB I1 0(f UHE II j! !IIII 飞茁血炽岸仙氏叹:眯谗电瞪-勒1讪罡XI栄谗电唄:顽呵厂 uu：JXLUU1、0岡；|丸JUlrijlTJUOlT二肚11010101110101010101；二1010101151110001.rjruinnimmjimimifuuL3、计分模块仿真图五、抢答器程序1顶层程序文件LIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY QDQ ISPORT(CLK1H Z, CLK2: IN STD_LO

6、GIC;CLR: IN STD_LOGIC;EN: IN STD_LOGIC;A,B,C,D: IN STD_LOGIC;ADD: IN STD_LOGIC;SUB: IN STD_LOGIC;A1,B1,C1,D1,E1: OUT STD_LOGIC;SOUND: OUT STD_LOGIC;QA,QB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-一下均为接数码管的输出NUMW,NUMG: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);J1,J2,J3,J4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);- 所有输入输出口

7、END QDQ;ARCHITECTURE ART OF QDQ IS-调用 QDJB,JSQ,JFQ 三个模块COMPONENT QDJBPORT(CLR: IN STD_LOGIC;CLK2: IN STD_LOGIC;EN: IN STD_LOGIC;SOUND: OUT STD_LOGIC;A,B,C,D: IN STD_LOGIC;A1,B1,C1,D1: OUT STD_LOGIC;NUMG: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);NUMW: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT

8、JSQ PORT(CLR,CLK,EN,CLK2: IN STD_LOGIC;E1: OUT STD_LOGIC;QA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);QB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COMPONENT;COMPONENT JFQ PORT(A: IN STD_LOGIC;B: IN STD_LOGIC;C: IN STD_LOGIC;D: IN STD_LOGIC;CLK: IN STD_LOGIC;ADD: IN STD_LOGIC;SUB: IN STD_LOGIC;J1: OUT STD_LOGIC_

9、VECTOR(3 DOWNTO 0);J2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);J3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);J4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END COMPONENT;BEGIN-与其他模块综合链接起来U1: QDJB PORT MAP(CLR=CLR,CLK2=CLK2,EN=EN,SOUND=SOUND,A=A,B=B,C=C,D=D,A1=A1,B1=B1,C1=C1,D1=D1,NUMG=NUMG ,NUMW=NUMW);U2: JSQ PORT MAP(CLR=

10、CLR,CLK=CLK1HZ,EN=EN,E1=E1,QA=QA,QB=QB, CLK2=CLK2);U3: JFQ PORT MAP(A=A,B=B,C=C,D=D,CLK=CLK1HZ,ADD=ADD,SUB=SUB, J1=J1,J2=J2,J3=J3,J4=J4);END ART;2、抢答过程程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY QDJB ISPORT(CLR: IN STD_LOGIC; CLK2: IN STD_LOGIC; EN: IN STD_LOGIC;SOUND: OUT STD_LOGIC; - 声音，抢到时会

11、响A,B,C,D: IN STD_LOGIC;A1,B1,C1,D1: OUT STD_LOGIC;四个 LED 灯，显示犯规警告，会亮NUMG: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-用于显示抢到的台数NUMW: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-显示犯规的台数END ENTITY QDJB;ARCHITECTURE ART OF QDJB ISSIGNAL G: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL W: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPRO1:PROCE

12、SS(CLR,A,B,C,D,EN) - 使用进程，用于判断哪路抢到BEGINIF CLR=1 THEN G=0000;SOUND=0;- 复位，归零ELSIF (EN=1 AND A=1 AND B=0 AND C=0 AND D=0)THEN-锁存输入信号，显示抢答者的序号G=0001;SOUND=1 AND CLK2;- 蜂鸣器接时钟，响ELSIF (EN=1 AND A=0 AND B=1 AND C=0 AND D=0)THENG=0010;SOUND=1 AND CLK2;ELSIF (EN=1 AND A=0 AND B=0 AND C=1 AND D=0)THENG=0100;

13、SOUND=1 AND CLK2;ELSIF (EN=1 AND A=0 AND B=0 AND C=0 AND D=1)THENG=1000;SOUND=1 AND CLK2;END IF;NUMG=G;END PROCESS;PRO2:PROCESS(EN,A,B,C,D)- 犯规显示BEGINIF(EN=0 AND A=1 AND B=0 AND C=0 AND D=0)THEN-对应台灯亮，犯规警告A1=1;B1=0;C1=0;D1=0;W=0001;ELSIF(EN=0 AND A=0 AND B=1 AND C=0 AND D=0)THEN A1=0;B1=1;C1=0;D1=0;

14、W=0010;ELSIF(EN=0 AND A=0 AND B=0 AND C=1 AND D=0)THEN A1=0;B1=0;C1=1;D1=0;W=0100;ELSIF(EN=0 AND A=0 AND B=0 AND C=0 AND D=1)THEN A1=0;B1=0;C1=0;D1=1;W=1000;END IF;NUMW=W;END PROCESS;END ARCHITECTURE ART;3、计时器程序 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JSQ ISP

15、ORT(CLR,CLK,EN,CLK2: IN STD_LOGIC;E1: OUT STD_LOGIC;- 时间到时会闪烁QA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);- 个位QB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);- 十位 END ENTITY JSQ;ARCHITECTURE ART OF JSQ ISBEGINPRO1:PROCESS(CLR,CLK,EN)VARIABLE TMPA:STD_LOGIC_VECTOR(3 DOWNTO 0);-中间量VARIABLE TMPB:STD_LOGIC_VECTOR(3 DOWNTO

16、 0);VARIABLE TMPC:STD_LOGIC;BEGINIF CLKEVENT AND CLK=1 THENIF CLR=1 THENTMPA:=0000;TMPB:=0010; TMPC:=0;-20sELSIF EN=1 THEN IF TMPA=0000 THENIF TMPB/=0000 THEN TMPA:=1001;- 变为 9TMPB:=TMPB-1;- 等到个位为 0 时十位 -1 ELSE TMPC:=1;- 时间到，报警 END IF;ELSE TMPA:=TMPA-1;END IF;END IF;END IF;QA=TMPA; QB=TMPB; E1=TMPC

17、AND CLK2;END PROCESS;END ART;4、计分器程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY JFQ ISPORT(A: IN STD_LOGIC;B: IN STD_LOGIC;C: IN STD_LOGIC;D: IN STD_LOGIC;CLK: IN STD_LOGIC;ADD: IN STD_LOGIC;SUB: IN STD_LOGIC;J1: OUT STD_LOGIC_VECTOR(3

18、 DOWNTO 0);J2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);J3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);J4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END JFQ;ARCHITECTURE ART OF JFQ ISSIGNAL AA: STD_LOGIC_VECTOR(3 DOWNTO 0);-SIGNALSIGNAL BB: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL CC: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL DD: STD_LO

19、GIC_VECTOR(3 DOWNTO 0);BEGINPOR1:PROCESS(ADD,SUB)BEGINIF(CLKEVENT AND CLK=1) THEN赋初值均为 5IF( ADD=1 AND SUB=1) THENAA=0101; BB=0101; CC=0101; DD=0101;- ELSIF(ADD=1 AND SUB=0) THENIF(A=1 AND B=0 AND C=0 AND D=0) THEN AA=AA+0001; BB=BB; CC=CC; DD=DD;ELSIF(A=0 AND B=1 AND C=0 AND D=0) THEN AA=AA; BB=BB+0

20、001; CC=CC; DD=DD;ELSIF(A=0 AND B=0 AND C=1 AND D=0) THEN AA=AA; BB=BB; CC=CC+0001; DD=DD;ELSIF(A=0 AND B=0 AND C=0 AND D=1) THEN AA=AA; BB=BB; CC=CC; DD=DD+0001;ELSE AA=AA; BB=BB; CC=CC; DD=DD;END IF;-加分程序elsIF(SUB=1 AND ADD=0) THENIF(A=1 AND B=0 AND C=0 AND D=0) THEN AA=AA-0001; BB=BB; CC=CC; DD=DD;ELSIF(A=0 AND B=1 AND C=0 AND D=0) THEN AA=AA; BB=BB-0001; CC=CC; DD=DD;ELSIF(A=0 AND B=0 AND C=1 AND D=0) THEN AA=AA; BB=BB; CC=CC-0001; DD=DD;ELSIF(A=0 AND B=0 AND C=0 AND D=1) THEN AA=AA; BB=BB; CC=CC; DD=DD-0001;ELSE AA=AA; BB=BB; CC=CC; DD=DD;END IF;ELS