硬件描算语言chapter4

1、第第4章章 Verilog HDL行为级描述行为级描述12/16/20211Microelectronics School Xidian University 行为级描述行为级描述是HDL语言特有的一种对于电路的描述方式，通过对于电路行为的计算机程序语言设计，综合工具可以生成相应的由基本单元构成的数字电路。行为级描述更像是固定模板的代码对应某个特性电路的形式，设计者通过改变模板的参数和内容从而实现电路的行为级描述，对于综合工具而言，生成的电路准确性也较高。（1）Verilog HDL行为级建模设计1bits D触发器module flipflop_d (data, clk, q); input

2、 data; input clk; output q; reg q; always(posedge clk) q=data; endmodule（2）Verilog HDL行为级建模设计8bits D触发器module flipflop_d (data, clk, q); input 7:0data; input clk; output 7:0q; reg q; always(posedge clk) q=data; endmodule12/16/20213Microelectronics School Xidian University 例4-2：带同步清零置位的模为10的加法计数器 mod

3、ule counter_10 (clk, clear, load, d, q7); input clk, clear, load; input 3:0 d; output 3:0 q7; reg 3:0 q7; always(posedge clk) begin if(! clear) q7 = 0; else if(! load) q7 = d; else if(q7 = 9); q7 = 0; else q7 = q7+1; end endmodule12/16/20214Microelectronics School Xidian University 12/16/20215Microe

4、lectronics School Xidian University 类别类别语句语句可综合性可综合性过程语句过程语句initial always语句块语句块串行语句块begin-end 并行语句块fork-join 赋值语句赋值语句连续赋值语句assign过程赋值语句=、=条件语句条件语句if-elsecase, casez, casex 循环语句循环语句forever repeat while for 编译向导语句编译向导语句defineincludeifdef,else,endif4.1 过程语句过程语句12/16/20216Microelectronics School Xidian

5、 University 4.1.1 initial过程语句过程语句initial begin 语句1; 语句2; 语句n;end例4.1-1：Verilog HDL用initial语句给D触发器赋初值 module d_ff(in,clk,q); input in; input clk; output q; reg q; initial q = 0; always(posedge clk) q=in; endmodule例4.1-2：Verilog HDL行为级描述异步清0、异步置1的D触发器module DFF1( d, clk, set, rst, q); input d, clk, se

6、t, rst; output q; reg q; always (posedge clk or negedge set or negedge rst) begin if (!rst) q = 0; /异步清0，低电平有效 else if (!set) q = 1; /异步置1，低电平有效 else q = d; end endmodule4.1.2 always过程语句和敏感事件表过程语句和敏感事件表12/16/20217Microelectronics School Xidian University always() 语句块;敏感信号可以分为两种类型：一种是电平敏感型，一种是边沿敏感型（1

7、）(a) （2）(posedge a) （3）(negedge a)12/16/20218Microelectronics School Xidian University 例4.1-3：利用敏感事件列表来对组合逻辑建模 module sel_adder_and_multiplier(y, a, b, sel); input a, b, sel; output y; wire 3:0 a,b; reg 7:0 y; always (a or b or sel) begin if (sel = 0) y = a+b; else y = a*b; end endmodule12/16/20219M

8、icroelectronics School Xidian University 例例4.1-4：3线线-8线译码器。线译码器。module decoder(din, dout); input 2:0 din; input 7:0 dout; reg7:0 dout; always (din) begin case (din) 3b000:dout = 8b00000001; 3b001:dout = 8b00000010; 3b010:dout = 8b00000100; 3b011:dout = 8b00001000; 3b100:dout = 8b00010000; 3b101:dout

9、 = 8b00100000; 3b110:dout = 8b01000000; 3b111:dout = 8b10000000; default:dout = 8b00000000; endcase endendmodule4.1.3 过程语句使用中信号类型的定义过程语句使用中信号类型的定义12/16/202110Microelectronics School Xidian University 在信号的定义形式方面，无论是对时序逻辑电路还是对组合逻辑电路进行描述，Verilog HDL要求在过程语句（要求在过程语句（initial和和always）中，被赋值信号必须定义为）中，被赋值信号必须

10、定义为“reg”类型。类型。例例4.1-7：Verilog HDL用用always描述两输入异或门。描述两输入异或门。module xor2(a, b, out); input a, b; output out; wire a, b; reg out; always ( a or b) out = ab;endmodule4.1.4 awlays过程语句中敏感事件的形式过程语句中敏感事件的形式12/16/202111Microelectronics School Xidian University （1）采用过程语句对组合电路进行描述时，需要把全部的输入信号列入敏感信号列表，且敏感信号列表不允

11、许存在边沿信号。例4.1-8：Verilog HDL用always语句描述4选1数据选择器module mux4_1(out,in0,in1,in2,in3,sel); input in0,in1,in2,in3;output out; input1:0sel; reg out; /被赋值信号定义为“reg”类型 always(in0 or in1 or in2 or in3 or sel) /敏感信号列表 case(sel) 2b00: out=in0; 2b01: out=in1; 2b10: out=in2; 2b11: out=in3; default: out=2bxx; endca

12、seendmodule12/16/202112Microelectronics School Xidian University 例4-2：带同步清零置位的模为10的加法计数器 module counter_10 (clk, clear, load, d, q7); input clk, clear, load; input 3:0 d; output 3:0 q7; reg 3:0 q7; always(posedge clk) begin if(! clear) q7 = 0; else if(! load) q7 = d; else if(q7 = 9); q7 = 0; else q7

13、 = q7+1; end endmodule（2）采用过程语句对时序电路进行描述时，需要把时间信号和部分输入信号列入敏感信号列表。异步清零和同步置位的模为10的加法计数器 module counter_10 (clk, clear, load, d, q7); input clk, clear, load; input 3:0 d; output 3:0 q7; reg 3:0 q7; always(posedge clk or negedge clear ) begin if(! clear) q7 = 0; else if(! load) q7 = d; else if(q7 = 9);

14、q7 = 0; else q7 = q7+1; end endmodule4.2 语句块语句块12/16/202113Microelectronics School Xidian University 4.2.1 串行语句块串行语句块begin:块名 块内声明语句; 语句1; 语句2; . . . 语句n;end 4.2.2 并行语句块并行语句块fork:块名 块内声明语句; 语句1; 语句2; 语句n;join 4.3 过程赋值语句过程赋值语句12/16/202114Microelectronics School Xidian University 4.3.1 阻塞赋值语句阻塞赋值语句变量

15、= 表达式;阻塞赋值语句的特点：（1）在串行语句块中，各条阻塞赋值语句将按照排列顺序依次执行；在并行语句块中的各条阻塞赋值语句则同时执行，没有先后之分。（2）执行阻塞赋值语句的顺序是，先计算等号右端表达式的值，然后立刻将计算的值赋给左边的变量，与仿真时间无关。4.3.2 非阻塞赋值语句非阻塞赋值语句变量 = 表达式;非阻塞赋值语句的特点：（1）在串行语句块中，各条非阻塞语句的执行没有先后之分，排在前面的语句不会影响到后面语句的执行，各条语句并行执行。（2）执行非阻塞赋值语句的顺序是，先计算右端表达式的值，然后等待延迟时间的结束，再将计算的值赋给左边的变量。12/16/202115Microel

16、ectronics School Xidian University 例例4.3-1：阻塞赋值语句例：阻塞赋值语句例程序（1）module DFF_C1(clk,q,in_1);inputclk,in_1;outputq;reg q;reg temp;always(posedge clk)begin temp=in_1; q=temp;endendmodule程序（2）module DFF_C2(clk,q,in_1);inputclk,in_1;outputq;reg q;always(posedge clk)q=in_1;endmodule 12/16/202116Microelectro

17、nics School Xidian University 例4.3-2：非阻塞赋值语句例程module DFF_C3(clk,q,in_1);input clk,in_1;output q;reg q;reg temp;always(posedge clk)begin temp=in_1; q=temp;endendmodule12/16/2021例4.3-3：阻塞赋值语句和非阻塞赋值语句对比例程（1）阻塞赋值语句module block(a, b, c, clk, sel, out); input a, b, c, clk, sel; output out; reg out, temp;

18、always (posedge clk) begin temp = a&b; if (sel) out = temp|c; else out = c; end endmodule（2）非阻塞赋值语句 module non_block(a, b, c, clk, sel, out); input a, b, c, clk, sel; output out; reg out, temp; always (posedge clk) begin temp = a&b; if (sel) out = temp|c; else out = c; end endmodule4.4 条件分支语

19、句条件分支语句12/16/20214.4.1 if条件分支语句条件分支语句形式1：if(条件表达式)语句块;形式2：if(条件表达式)语句块1; else语句块2;形式3：if(条件表达式1)语句块1;else if语句块2;. . .else if(条件表达式i) 语句块i;else 语句块n;12/16/202119Microelectronics School Xidian University 例4.4-1：if-else使用例程（1）module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always(a,b,s

20、el) begin if(sel) out=a; else out=b; end endmodule4.4.2 case条件分支语句条件分支语句12/16/202120Microelectronics School Xidian University case(控制表达式) 值1: 语句块1; 值2: 语句块2; . . . 值n: 语句块n; default: 语句块n+1; endcase表表4.4-1 case分支语句的真值表分支语句的真值表case01xz0100010100 x0010z0001module non_latch_case(a,b,sel,out);input a,b;

21、input 1:0sel;output out;reg out;always(a,b,sel)case(sel) 2b00:out=a; 2b01:out=a; 2b10:out=b; 2b11:out=b;default:out=0;endcaseendmodulemodule non_latch_case(a,b,sel,out);input a,b;input 1:0sel;output out;reg out;always(a,b,sel)case(sel) 2b00: 2b01:out=a; 2b10: 2b11:out=b;default:out=0;endcaseendmodul

22、e12/16/202121Microelectronics School Xidian University 例例4.4-5：用：用case语句描述语句描述BCD数码管译码数码管译码module BCD_decoder(in, out); input 3:0 in;output 6:0 out; reg 6:0 out; always (in) begin case(in) 4d0: out = 7b1111110; 4d1: out = 7b0110000; 4d2: out = 7b1101101; 4d3: out = 7b1111001; 4d4: out = 7b0110011; 4

23、d5: out = 7b1011011; 4d6: out = 7b1011111; 4d7: out = 7b1110000; 4d8: out = 7b1111111; 4d9: out = 7b1111011; default: out = 7bxxxxxxx; endcase end endmodule12/16/202122Microelectronics School Xidian University 例4.4-9：case语句语句中default（1）会产生锁存器的case语句module latch_case(a,b,sel,out);input a,b;input 1:0s

24、el;output out;reg out;always(a,b,sel)case(sel) 2b00:out=a; 2b11:out=b;endcaseendmodule（2）不会产生锁存器的case语句module non_latch_case1(a,b,sel,out);input a,b;input 1:0sel;output out;reg out;always(a,b,sel)case(sel) 2b00:out=a; 2b11:out=b; default:out=0;endcaseendmodulecasex和casez12/16/202123Microelectronics School Xidian University