WATTraining实用教案

1、OutlineWhat is WATTest PatternHardware SystemSoftware SystemTest Parameter第1页/共75页第一页，共76页。 WAT standard forWafer Acceptance TestWhat is WAT?第2页/共75页第二页，共76页。What kind of work?An electrical test system, non-productivity activity WAT is an electrical test system for process goodness monitor. Device c

2、haracteristics:resistor, capacitor, interconnection, continuity, spacing, insulation, leakageWAT is the primary quality element for a foundry FAB ( the quality assurance for wafer output) WAT characteristics: DC force and measurement, Automation, high throughput, precision, samplingWhat is WAT?第3页/共

3、75页第三页，共76页。Why WAT Monitor Process Window. Check Design Rule. Control the Process Parameters(SPC). Debug the Process Error. Reliability Characterization. Device Modeling for Circuit Design. Develop next Generation.What is WAT?第4页/共75页第四页，共76页。Test Pattern Test key: WAT just tests the Test Key some

4、was put inside chip, for design rule check, yield monitor and process qualification and development. some was put on scribe line. These test key will be destroyed after die saw.12322第5页/共75页第五页，共76页。Test Key ATest Key BTest Key DTest Key CTest Key ETest Key FSite & Test KeyTest Pattern第6页/共75页第六

5、页，共76页。TESTER 1Test HeadProberWaferProbe cardChuckController1System sketch map Hardware System第7页/共75页第七页，共76页。WAT (Wafer Acceptance Test): electrical parameter test on specially designed test structure on scrub lanes, such as all kinds of transistors, resist test patterns, leakage/breakdown test pa

6、tterns, to decide whether the wafer go through an normal process, and shippable to customer.Test Tools: TEL P8XLProber stationKeithley S630Auto-tester (all SMU: Current accuracy: 0.1fA)Signatone S1170Manual ProberKeithley S4200Manual tester (One SMU: Current accuracy: 0.1fA)Agilent 4284C-V tester (M

7、anual)Agilent 4156Manual tester (all SMU: Current accuracy: 10fA) Hardware System第8页/共75页第八页，共76页。Agilent Testing system Automatic Tester4072A (Agilent) Automatic ProberP8-XL (TEL) Server (workstation)HP Prober Card Hardware System第9页/共75页第九页，共76页。Agilent 4072 + TEL P8-XLTester Head4072AControllerSc

8、reenWaferLoaderTouchPannelAuto WaferChanger Hardware System第10页/共75页第十页，共76页。 Auto Tester FunctionForce voltage, current.Measure voltage, current.Capacitance measure.Control prober movingA switch matrix to provide more than 48 pin output. Hardware System第11页/共75页第十一页，共76页。 Agilent Tester 4072AWorkst

9、ation8114A4284Power Supply81110Cooling FanSystem CabinetTest headDiag BoardCPUInputSelector8 AUXPorts8 SMUGNDUPulse Switch6 HF PortMatrixOptical Interface Hardware System第12页/共75页第十二页，共76页。Test Head of 4072A48 Pin48 inputExtended PathAUX PortHF PortPulseSwitch Port Hardware System第13页/共75页第十三页，共76页。

10、Auto Prober FunctionWafer load, unload & transfer to chuck.Prober Card Wafer pre-alignment, precise alignment.Test Line locate.Chuck up(probed)Chuck down(un-probed) Hardware System第14页/共75页第十四页，共76页。TEL Prober P8-XL Hardware System第15页/共75页第十五页，共76页。Prober & Prober Card Hardware System第16页/共

11、75页第十六页，共76页。Prober Card Bird CageStructureDirect Dockingstructure Direct Docking+4062UX4071/72A Hardware System第17页/共75页第十七页，共76页。Prober Card made in SMIC Hardware System第18页/共75页第十八页，共76页。SACC: Setup Probe Card & Change Probe Card Hardware System第19页/共75页第十九页，共76页。SACC Hardware System第20页/共75页

12、第二十页，共76页。Main programTPL filePut Cassette on P8Use controller toAccess Main programWAT serverSelect Test PlanWAT serverInitializationController: store raw dataProber: ProbingTester: Force and measureTest Finish load data to serverWAT Operating Flow Software System第21页/共75页第二十一页，共76页。Software of Aut

13、o Tester Agilent SPECS SPECS is a software to develop and execute a wafer measurement program Semiconductor Process Evaluation Core Software Software System第22页/共75页第二十二页，共76页。SPECS WorkCIMOperator ModeEngineering ModeRemote ExecutionAlgorithm LibraryRun Time AnalysisDatabaseSPECS FrameworkTest Plan

14、NavigatorWaferSpecificationDieSpecificationProbeSpecificationTestSpecification Software System第23页/共75页第二十三页，共76页。Test parameters category:1.MOS Transistor: N-MOS, P-MOS, 3.3V N-MOS , 3.3V PMOS2.Gate Oxide (GOI)3.Fiels oxide transistor4.Junction Test 5.Rs (Sheet resistance)6.Rc (Contact resistance)7

15、.Continuity & Bridging Test8.Capacitor TestTest Parameter第24页/共75页第二十四页，共76页。MOS transistor (N type as example):Transistor Type:Typical NMOS (10/0.18, 10/0.2, 10/0.16), Long channel NMOS (10/10), Narrow width NMOS (0.22/10), Small NMOS (0.22/0.18)3.3V NMOS Transistor: Typical NMOS (10/0.35), Lon

16、g channel NMOS (10/10), Narrow width NMOS (0.22/10)3.3V NMOS Transistor without Dummy AA (0.22/10)Primary Parameters: Vt (VTLIN, VTGm, VTSAT), IDSAT, IOFF, BVDSecondary Parameters: ISUB, DIBL, GAMMA, SWING,Gleak, Gm, Isubmax, Isubvg, Gleak2, SUBVTSLP, Vt1, Vt2, MFAC1, MFAC2, BETATest Parameter第25页/共

17、75页第二十五页，共76页。 Typical NMOSa)Purpose: To monitor the electrical property of typical sub rule transistorb)Design: L= 0.20,0.18,0.16 for 0.18 technologyAAL100.37520poly85dummy AA 5um0.160.16603080N+PWS/L0.22Test Parameter第26页/共75页第二十六页，共76页。Long channel NMOSa)Purpose: To monitor the electrical propert

18、y of long channel transistor b)Design: L= 10 for 0.18 technology AA10L2060N+2PWS/L80300.16Test Parameter第27页/共75页第二十七页，共76页。Narrow width NMOS a) Purpose: To monitor the electrical property of narrow width transistor b) Design: W= 0.22 for 0.18 technology W2030101088060PWS/LN+0.22Test Parameter第28页/共

19、75页第二十八页，共76页。Small NMOS a) Purpose: To monitor the electrical property of small dimension transistorb) Design: L= 0.18 W= 0.22 for 0.18 technology 60LW10200.160.5PWS/L10530180Test Parameter第29页/共75页第二十九页，共76页。Narrow width NMOS without dummy AAa) Purpose: To monitor the electrical property impacted

20、caused by dishing effect of STI CMPb) Design: W= 0.22 for 0.18 technology 60LW10200.220.5PWS/L10530180AAAATest Parameter第30页/共75页第三十页，共76页。Transistor WAT parameters and test condition:1. VTGm_N:VD=0.05V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNextrapolate to VG at max slope, measure VTGm_N =

21、VG(INTERCEPT) - 0.5*VDId/Gm vs VgId/Gm vs Vg00.0010.0020.0030.0040.00500.511.522.533.54Vg(V)Vt=X-intercept - 0.5*0.05V (for NMOS)Vt=X-intercept - 0.5*0.05V (for NMOS)Id(A)Gm(mho)X-intercept (L1X)Max GmIn linear region:In Saturation region:When Id =Idsat, Vd=VG-Vth, and So, ddthgoxndVVVVCLWI212)(21th

22、GoxndsatVVCLWIdoxnGdmVCLWVIg5 . 0)(21)(dthgmdthGGdVVVgVVVVIIdd0.5VgIVVmdgthTest Parameter第31页/共75页第三十一页，共76页。2. VTLIN_N:VD=0.05V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNMeasure VTLIN_N=VG ID=0.1uA*(W/L)To simplify the calculation, the transistor was considered turned on when ID=0.1uA*(W/L)Ty

23、pical Value:VTLIN_N_10/10 = 0.37VVTLIN_P_10/10= -0.44VVTLIN_N_10/0.18= 0.44VVTLIN_P_10/0.18 = -0.5VVTLIN_N_0.22/10 = 0.31VVTLIN_P_0.22/10 = -0.41VVTLIN_N_0.22/0.18 = 0.36VVTLIN_P_0.22/0.18 = -0.5VVTLIN_N3.3_10/10 = 0.68VVTLIN_P3.3_10/10 = -0.73VVTLIN_N3.3_10/0.35 = 0.72VVTLIN_P3.3_10/0.35 = -0.68VVT

24、LIN_N3.3_0.22/10 = 0.56VVTLIN_P3.3_0.22/10 = -0.68V3. VTSAT_N:VD=1.8V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNMeasure VTSAT_N = VG ID=0.1uA*(W/L)VD=VDDN, to make sure that the transistor is working at the saturation statusTest Parameter第32页/共75页第三十二页，共76页。4. IDSAT_N: VD=VG=VDDN=1.8V, VS=VB=0

25、, Measure IDSAT_N=ID (then divide by W in some calculation)Typical Value:IDSAT_N_10/0.18 = 6mAIDSAT_P_10/0.18 = -2.59mA(600 uA/um)(-259 uA/um)IDSAT_N_0.22/10 = 4uAIDSAT_P_0.22/10 = -1.1uAIDSAT_N_0.22/0.18 = 180uAIDSAT_P_0.22/0.18 = -60AIDSAT_N3.3_10/0.35 = 6mAIDSAT_P3.3_10/0.35 = -3mAIDSAT_N3.3_0.22

26、/10 = 7.58uAIDSAT_P3.3_0.22/10 = -1.61uA2)(21thGoxndsatVVCLWITest Parameter第33页/共75页第三十三页，共76页。5. IOFF_NVD=1.1*1.8V, VG=VS=VB=0, Measure IOFF_N = ID (then divide by W in some calculation)Typical Value:IOFF_N_10/0.18 = 60 pAIOFF_P_10/0.18 = -30 pAIOFF_N3.3_10/0.35 = 60 pAIOFF_P3.3_10/0.35 = -35 pA6.

27、BVD_NVG=VS=VB=0V, VD = 1.8 To 3*VDDN, whereas, VDDN=1.8V or 3.3V, Measure BVD_N=VD ID=0.1uA*WTypical Value:BVD_N_10/0.18 = 4VBVD_P_10/0.18 = -5.21VBVD_N3.3_10/0.35 = 7VBVD_P3.3_10/0.35 = -6.99VTest Parameter第34页/共75页第三十四页，共76页。7. ISUB_NVD=1.1*1.8V, VS=VB=0, VG = 0.2*1.8V to 1.1*1.8V, Find ISUB_N (MA

28、X)(then, divided by W in some calculation)The substrate current in an n-channel MOSFET results from hole generation by impact ionizations induced by the channel electrons traveling from source to drain. Assuming impact ionization occurs uniformly in the pinch off region (near the drain), the substra

29、te current, Ibs, may be written as Ibs=Id Lwhere = ionization coefficient L= length of pinch off regionWith Vg, Ibs , and reaches a miximum value, then decrease.The initial Ibs increase is due to the increase in Id with Vg. However, as Vg goes up, the lateral field decreases, causing a reduction in

30、. Thus, the peak substrate current occurs when the two competing factors cancel out, usually at 0.5Vd.Typical Value:ISUB_N_10/0.18= ( 1.6 uA )ISUB_P_10/0.18 = ( -0.013 uA )Test Parameter第35页/共75页第三十五页，共76页。 8. DIBL (Drain Induced Barrier Lowering)VTLINVD=0.05V, VS=VB=0, VG = 0 to 0.8*VDDNMeasure VTL

31、IN=VG ID = 0.1A*(W/L)VTSATVD=1.1*VDDN, VS=VB=0, VG = 0 to 0.8*VDDNMeasure VTSAT=VGID = 0.1A*(W/L)DIBL= (VTLIN-VTSAT) / (1.1*VDDN-0.05)Threshold variation is caused by the increased current with increased drain voltage, as the applied drain voltage controls the inversion layer charge at the drain, th

32、ereby competing with the gate voltage. In the weak inversion regime, there is a potential barrier between the source and the channel region. The height of this barrier is a result of the balance between drift and diffusion current between these two regions. If a high drain voltage is applied, the ba

33、rrier height can decrease, leading to an increase drain current. Thus the drain current is controlled not only by gate voltage, but also by the drain voltage.Test Parameter第36页/共75页第三十六页，共76页。 9. GAMMA_N ( : body effect) VD=0.05V, VS=0, VB=-1.5*1.8, VG=0 to 1.1*1.8 Measure VTLIN1_N = VG ID=0.1uA*(W/

34、L) the threshold voltage with substrate bias ( VB) =0.443744GAMMA_N=ABS (VTLIN1_N-VTLIN_N) / ASB(VB)+2* 1/2-2* 1/2 Since, VT = GC-QB/Cox-2 B-Qox/Cox = VFB-2 B+ SQRT(-2 B+VB) Where: VFB= GC-Qox/Coxand =SQRT(2siqNB)/Cox VTLIN1=VFB-2 B+ SQRT(-2 B+VB)VTLIN = VFB-2 B+ SQRT(-2 B) =(VTLIN1-VTLIN)/SQRT(-2 B

35、+VB)- SQRT(-2 B)Typical Value:GAMMA_N_10/10 = 0.5 V1/2GAMMA_P_10/10 = 0.57 V1/2Test Parameter第37页/共75页第三十七页，共76页。10. SWING_NVD=0.05V, VS=VB=0, VG = 0 to 1.8V, Measure VG1 ID = 10 nA *(W/L) VG2 ID = 0.1 nA * (W/L)SWING_N = 500* (VG1-VG2)In the week inversion (or sub-threshold) regime, the transistor

36、conducts a very small sub-threshold current, and the drain current depends exponentially on the gate-source voltage. To measure the sub-threshold slope, SS, when VD=0.05V, is defined as:Ileak1= 10nA*(W/L)Ileak2=0.1nA*(W/L)VG2 VG1SUBVTSLP=(slope)-1=(VG1-VG2 )/log (Ileak1) log (Ileak2) = (VG1-VG2 )/ l

37、og(Ileak1/Ileak2) V/dec= (VG1-VG2 )/ log(10/0.1) V/dec= (VG1-VG2 )/ 2 V/dec= 500* (VG1-VG2 ) mV/decTypical Value:SWING_N_10/0.18= 88 mV/decSWING_P_10/0.18= ( -93 mV/dec)Test Parameter第38页/共75页第三十八页，共76页。11. Gleak_NVS=VD=VB=0,VG= - VDDN=-1.8V, Measure IG. If 50nA, consider Transistor fail the test, s

38、kip all rest transistor tests12. Gm_NMax slope of ID vs VG VB=013. VsubvgVD= 1.1*VDDN,VB=VS=0,VG=0.2*VDDN to 0.7*VDDNMeasure VG max ISUBTest Parameter第39页/共75页第三十九页，共76页。14. DELTA_LEXTRACT FROM NE2 20/0.36 & 18N1 20/0.18 VS=VB=0,VD=0.05,VG=VT0+0.2*VDDN & VT0+0.4*VDDN, MEASURE Rch=VD/ID FOR E

39、ACH DEVICE, DELTA_L=X-VALUE FOR INTERCEPT OF 2 LINES (Rch vs Ldrawn)The I-V characteristics of an MOS transistor operating in the linear region can be expressed as:Ids= Cox (Weff / Leff) (VGS-Vt-1/2Vds)Vdswhere Weff=Wmask-W; Leff=Lmask- L and Rchan=Vds/Ids=Leff / Cox Weff (VGS-Vt-1/2Vds)The effectiv

40、e channel length, Leff, differs from the mask defined channel length,L, due to the source and drain junction encroachment under the gate as shown in the picture.The measurement is performed in the linear region, in order to eliminate channel length modulation.LeffLTest Parameter第40页/共75页第四十页，共76页。W

41、accounts for any process bias such as print bias, etch bias, birds beak and lateral diffusion of channel stop implant.L accounts for print bias, etch bias, birds beak and lateral diffusion of source-drain dopant. Measured resistance Rm= VDS/IDS = Rext +Rchan If taking Rext (Exsert Resistor) into con

42、sideration. Then Rm = Rext + (Lmask- L )/ Cox Weff (VGS-Vt-1/2Vds) Condition: Weff W, to avoid narrow channel effect, and VDS (VDS=6V) to minimize short channel Vt dependence on LeffAssumption: Each transistor has the same value of Rext. For adjacent transistors on a single chip with the same size o

43、f source and contact openings, this assumption is considered reasonable.RmVGS=Vt0+ 0.2VDDNVGS=Vt0+ 0.4VDDN L 0.18 0.36RextTest Parameter第41页/共75页第四十一页，共76页。 15. Channel Length Modulation Channel length modulation is caused by the increase of the depletion layer width at the drain as the drain voltag

44、e is increased. This leads to a shorter channel length, and an increased drain current, The channel-length-modulation effect typically increase in small devices with low-doped substrates. An extreme case of channel length modulation is punch through where the channel length reduces to zero. Proper s

45、caling can reduce channel length modulation, namely by increasing the doping density as the gate length is reduced.SaturationTriodeSlop=1/rIDSIDS2IDS1VDS1 VDS2VDS is chosen sufficiently large (VGS-Vt), so that the transistor is in saturation regionNow, from the saturation drain current expression an

46、d with VGS=Vt+1, we have the equation below from which can be determined.IDS2/IDS1= (1+VDS2) / (1+VDS1) -VA=-1/Test Parameter第42页/共75页第四十二页，共76页。 16. SUBVTSLP (Similar to SWING)VS=VB=0, VD= 1.1*VDDN, VG=VT0-0.2. Measure ID, get Ileak1VS=VB=0, VD= 1.1*VDDN, VG=VT0-0.3. Measure ID, get Ileak2SUBVTSLP

47、= 100 / LOG( ILEAK1/ILEAK2) In the week inversion (or sub-threshold) regime, the transistor conducts a very small sub-threshold current, and the drain current depends exponentially on the gate-source voltage. To measure the sub-threshold slope, SS, when VD=1.1VDDN, is defined as:Ileak1=0.1nA*(W/L)Il

48、eak2=0.01nA*(W/L)VG2 VG1SUBVTSLP=(slope)-1=(VG1-VG2 )/log (Ileak1) log (Ileak2) =0.1/log(Ileak1/Ileak2) V/dec =100/ log(Ileak1/Ileak2) mV/decTest Parameter第43页/共75页第四十三页，共76页。17. Intrinsic Trans-conductance, =(Max slope of IDS VS VGS)/VDS*(L-L)/WIn linear region: and then, = nCox = (gm/VDS)*(L/W)DSD

49、StGSoxnVVVVCLWI21DSdoxnGdmVCLWVIgTest Parameter第44页/共75页第四十四页，共76页。Gate Oxide Integrity (GOI)Test structure type: Pwell_Bulk, Pwell_Poly Edge, Pwell_Poly Finger, Pwell_STI EdgeNwell_Bulk, Nwell_Poly Edge, Nwell_Poly Finger, Nwell_STI EdgeTest parameters: TOX/PW_BK, ILOX/PW_BK, BVOX/PW_BK, BVOX/PW_PE

50、, BVOX/PW_ST, BVOX/PW_PFTOX/NW_BK, ILOX/NW_BK, BVOX/NW_BK, BVOX/NW_PE, BVOX/NW_ST, BVOX/NW_PFTest Parameter第45页/共75页第四十五页，共76页。 P-well GOX bulk type with poly edge: Pwell_Bulka)Purpose: To monitor gate oxide integrity on Pwell b)Design: Area=100*70 for 0.18 technology N+ Poly1157570100P-WellellBVOX/

51、PW_PE:VB=0V, VG=-1.8V to 4*(-1.8)V,Measure: BVOX/PW_PE=VG IG=-1uATest Parameter第46页/共75页第四十六页，共76页。 P-well GOX bulk type with field edge : Pwell_Bulka)Purpose: To monitor gate oxide integrity on P-well with field edgeb)Design: Area=100*70 for 0.18 technology P-well AA1007075N+ poly115Test Parameter第

52、47页/共75页第四十七页，共76页。1. TOX/PW_BK:100KHz, 45mV, VG=GND, VB=1.1*1.8V,Measure: CAP, then TOX/PW=3.9*8.85418*7000/CAP2. ILOX/PW_BK:VG=-1.8V, VB=0V,Measure ILOX/PW_BK=IG3. BVOX/PW_BK:VB=0V, VG=-1.8V to 4*(-1.8)V,Measure: BVOX/PW_BK=VG at IG=-1uATest Parameter第48页/共75页第四十八页，共76页。 P-well GOX square type wit

53、h field edge: (GOI square pattern with Field edge on P-well)a)Purpose: To monitor gate oxide integrity on P-well with square field edgeb)Design: AA L/S=5/2 for 0.18 technology N+ polyP well AA75110BVOX/PW_ST:VB=0V, VG=-1.8V to 4*(-1.8)VMeasure: BVOX/PW_ST=VG IG=-1uATest Parameter第49页/共75页第四十九页，共76页。

54、 P-well GOX finger type with poly edge: (GOI pattern on P-well with finger type poly edge pattern )a)Purpose: To monitor gate oxide integrity on P-well with poly edge b)Design: L=0.18 S=0.25 N=360 for 0.18 technology N+ polyPW AA11570267110BVOX/PW_PF:VB=0V, VG=-1.8V to 4* (-1.8)VMeasure BVOX/PW_PF=V

55、G IG=-1uATest Parameter第50页/共75页第五十页，共76页。Field TransistorTest structure type: N-Filed Poly gate transistor , N-Filed Metal gate transistor P-Filed Poly gate transistor , P-Filed Metal gate transistor Test parameters: VTF_P1_N, VPTF_P1_N, VTF_M1_N, VPTF_M1_NVTF_P1_P, VPTF_P1_P, VTF_M1_P, VPTF_M1_PDr

56、ainSourceGateP_SUBTest Parameter第51页/共75页第五十一页，共76页。N-Filed Poly gate transistor: (N+ to PW junction leakage, finger type AA )Purpose: To monitor the field oxide quality by field Vt test Design: W= 0.28 for 0.18 technology Poly2 or M1GateDrainSourcePsubActive-active spaceAAN+11030W151515PWActive-act

57、ive space is set 0.28m as per design rule. The poly2 or M1 overlap of diffusion is 0.28m.Test Parameter第52页/共75页第五十二页，共76页。1. VTF_P1_NVD=2V, VS=VB=0V, VG=0V to 10VMeasure: VTF_P1_N = VG ID=0.1uA2. VPTF_P1_NVG=2V, VS=VB=0V, VD=0V to 10VMeasure: VPTF_P1_N = VD ID=0.1uA3. VTF_M1_NVD=2V, VS=VB=0V, VG=0V

58、 to 10VMeasure: VTF_M1_N = VG ID=0.1uA4. VPTF_M1_NVG=2V, VS=VB=0V, VD=0V to 10VMeasure: VPTF_M1_N = VD ID=0.1uATest Parameter第53页/共75页第五十三页，共76页。JunctionTest structure type: N+/P-well junction finger type, N+/P-well junction bulk type P+/N-well junction finger type, P+/N-well junction bulk type Test

59、 parameters: CJ/PW_F1.8, IJ/PW_F1.8, BJ/PW_F1.8CJ/PW_B1.8, IJ/PW_B1.8, BJ/PW_B1.8Test Parameter第54页/共75页第五十四页，共76页。 N+/P-well junction finger type : (N+ to PW junction leakage, finger type AA )a)Purpose: To monitor the junction leak from N+ to Pwell with finger pattern b)Design: L=0.22 S=0.28 N=190

60、for 0.18 technology AA65N+PW75100N pitch2Test Parameter第55页/共75页第五十五页，共76页。1. CJ/PW_F1.8100kHz, 45mV, VD=GND, VB=0V,Measure: CJ/PW_F1.8=CAP2. IJ/PW_F1.8VD=1.1*1.8V, VB=0VMeasure: IJ/PW_F1.8=ID3. BJ/PW_F1.8VB=0V, VD=1.8V to 15VMeasure: BJ/PW_F1.8=VD ID=1uATest Parameter第56页/共75页第五十六页，共76页。 N+/P-well junction bulk type : (N+ t