16BITKOGGE-STONETREEADDER

1、116 bit kogge-stone tree adderhttp:/ abstract introduction why tree adder? theory project details summary of results lessons learned cost analysis conclusionhttp:/ we designed 16 bit kogge-stone tree adder - the most commonly used parallel prefix carry-lookahead adder topology. 200mhz clock frequenc

2、y area 1000*600 um2 power density ami06 technologyhttp:/ why? - minimum logic depth, wide wiring channels, regular structure and large fanout points. prefix adder structures1b1a1p1g1g0:0s2b2p2g2g1:0a2s3b3a3p3g3g2:0s4b4p4g4g3:0a4cing0p01: bitwise pg logic2: group pg logic3: sum logicc0c1c2c3coutc4htt

3、p:/ details17 pin outs 33 input d-flip flops and 17 output d-flip flopscreate schematic and layout for 16 bit tree addertest schematic using test benchrun drc and lvs to verify the designhttp:/ block diagram1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:143:04:15:26:37:48:59:610:711:812:913:1

4、014:1115:124:05:06:07:08:19:210:311:412:513:614:715:82:0012345678910111213141515:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0http:/ path calculationtphl = 5ns/(14+3) = .29nshttp:/ of actual wn & wphttp:/ reporthttp:/ reporthttp:/ reporthttp:/ analysis estimate amount of time spent o

5、n project:- verifying nc verilog5 hrs- verifying timing10 hrs- layout40 hrs- post extracted timing10 hrshttp:/ learned start early work in group study previous projects seek advice from dr. parent and previous students save time for debugging error http:/ we designed and implemented a 16 bit kogge-stone tree adder that operates at 200mhz in an area of 1000*600 um2http:/ thanks to cadence design systems for th