电子设计自动化中英文翻译毕业论文.doc

电子设计自动化中英文翻译 毕业论文附录B 翻译原文Electronic design automationKeyword EDA; IC;VHDL language; FPGAPROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then, as the number of logic gates per chip passes the million marks, verification of a designs correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money.PARLEZ-VOUS SUPERLOG?A system on a chip comprises both circuitry and the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chips functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is given to the pro- grammars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virology or VHDL, while the part that will end up as software is most often described in the programming language C or C+. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion.It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right through to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing language to meet system-on-chip needs. Among the candidates for extension were C, C+, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then they spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functions like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directly.It is important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently Co-Design identified a number of electronic design automation companies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process.ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a modeling platform that extends the capabilities and advantages of C/C+ into the hardware domain has been proposed as an alternative. Such large and powerful companies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote their version of the next-generation design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for developing SystemC was straightforward, according to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange system-level IP and executable specifications, and the electronic design automation industry could develop interoperable tools. Supporters of SystemC believe that the would-be standard has to be based on C+ because it allows capabilities to be added to it without leaving the language standard, Kunkel told JEEE Spectrum. Most software developers use C+ and many systems developers use C+ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardware using the language.The developers of SystemC have solved that problem by defining new C+ class libraries and a simulation kcrne1 that bring to C+ all of the capabilities needed to describe hardware. These new classes implement new functionality, explained Kunkel. For example, bit vectors-strings of zeros and ones-and all the operations that you would do on them. The SystemC developers also provided a class of signed and unsigned numbers, the notion of a signal, and other concepts needed to model hardware. There are still some holes, however. For example, it is still not possible to synthesize a gate-level netlist from a SystcmC description. Rut synthesis tools for SysteniC would he a natural result of broad acceptance of the language within the user community, according to Kunkel. It remains to be seen whether SystemC or Superlog wins out in the end. Least desirable would be an outcome like the impasse between Virology and VHDL, in which both prevailed, forcing electronic design automation vendors to support both platforms in a wasteful duplication of effort. THE VERIFICATION NIGHTMARE If todays complex ICs are tough to design, they are very much tougher to verify. A variety of tools are available, each with its pros and cons. Emulation translates a design into field-programmable gate arrays (FPGAs). Presumably, if the array works as planned, the final chip will also. The emulation platform also enables designers to try 0111 the software that will run on the ASIC. The approach, though, is slow. Typical emulation systems run at a few megahertz. At roughly one million cycles per second, designers arc not getting cnough performance out of their emulation systems to verify or understand some of the things that are going on with video generation or high bandwidth communications, said John Gallagher, director of marketing for Synplicity Inc., Sunnyvale, Calif. They must process a large number of operations to ensure their functionality is correct, he added. The reason that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few high-end FPGAs having over one million gates running at 100 MHz. Typically, a million FPGA gates translates into 200 000 ASIC gates. Putting nine such chips on a board in a three-by-three array allows designers to represent up to 1.8million ASlC gates. And routing delays are greatly curtailed because each chip is no more than two hops away from any other chip in the array. The company% product, called Certify, is not intended to compete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. Certify handles three fundamental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC gates. Then it does timing analysis. We havent just linked together the different tools,” he explained. We have taka our synthesis algorithms, between the partitioning capabilities, and laid the timing analysis across that. In addition to emulation, two complementary approaches to design verification are simulation and model checking, a type of formal verification. Simulation applies vectors to a software model of a design and checks to sec if the output has the correct value. The approach is straightforward, but is becoming increasingly tortuous as designs become more complicated and the number of possible test vectors mushrooms. So recently, electronic design automation companies have been turning to model checking to prove that designs are correctly done. The sticking point with model checking is its great difficulty of use. It is not for most engineers, said Simon Napper, chief operating officer OF Innol-ogic Systems Inc., San Jose, Calif. The usage model is very difficult-it checks properties. But the designer isnt familiar with what P property is-he is used to simulation and static timing. As a remedy, InnoLogic developed a symbolic simulation tool, which blends simulation and formal verification. It is a Virology simulator except instead of sending Is and Os through the logic, the too1 propagates symbol or symbols plus binary values.The user gains improved functional coverage dong with much faster verification. To illustrate, to completely verify a fourbit adder would require 256 binary vectors-and take 256 simulation cycles. With symbols, it takes just one cycle.Just as with formal verification, there are limits to the complexity of the circuits that symbolic simulation can completely verily. Both have trouble with multipliers, for example. A model checker will grind and grind and never produce a result, explained Napper. But in our tool we take some symbol inputs and switch them to binary values, that reduces the job from a 32- to a 16-bit multiplier. And we report to the user that we were able to verify the upper the operands. InnoLogic has announced two Versifies of symbolic simulation. ESI-XV verifies designs written in Virology. EXP-CV is meant for custom designs and memory blocks. THE TIME IS RIGHT Though the design of ICs with semiconductor geometries below 0.25 pm face challenges throughout development, some of the biggest hurdles occur during physical design, when the gates are placed on the chip and the interconnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interconnects cannot be ignored, as they were in older, larger technologies. Crosstalk between interconnects; now closer together, must also be controlled. Several iterations through synthesis and placement may be necessary to achieve the required timing, if it can be accomplished at all. The solution proposed by Monterey Design Systems Inc., Sunnyvale, Calif., is called global design technology. This proprietary computing approach simultaneously explores, analyzes, and optimizes all aspects of the physical design. The tint product containing the technology is Dolphin, which was announced in April of last year. Dolphin simultaneously places and router each gate and flip-flop using the results or the analysis and maintaining all specified constraints. (Most place- and-route tools sequentially analyze the layout for each type of constraint.) It performs timing and logic optimization for every placement move.Timing closure is top priority for developers of the Blast Fusion physical design system from Magma Design Automations., Cupertino, Calif. Its methodology, called FixedTiming, brings timing within specified limits without iterating between synthesis and physical design .Basically, he approach fixes timing first, then adjusts cell sizes to achieve the timing requirements. Varying the cell sizes always he tool to supply the right drive strength or the load.EDA ON THE WEB As established electronic design automation companies try to sort out how to utilize the internet in their product Inks, smaller, more agile companies and start-ups arc coining up with innovative products and services, mainly in the areas or design management. A pioneer in this area is Synchronicity Inc., a virtual company headquartered in Marlboro, Mass. Synchronicity is now being joined by other companies seeking to use the internet to advantage. The concern of CCAES.COM, Milpitas, Calif a provider of Web-based engineering tools for; design automation, is the extraction of useful information about ICs, chip sets, and boards from suppliers Web sites. The issue, according to Michael Bitzko, president of the company, is that designers of products based on there components need to be able to obtain information about them quickly and route it to their engineering, manufacturing, and procurement departments as quickly as possible. In a nutshell,” said Bitzko, people used to take weeks to get data sheets. Then along cane the Web and PDF-formatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards, information from PDF documents must often be reentered-a costly and time-consuming process when time to infarct is a concern. CCAES.COMs products are based on the electronic component interchange (ECIX) standard developed by EDA standards organization SI, Austin, Texas, and on the Extensible Markup Language (XML), that allows the creation or Web-bask documents having (more functionality than with the conventional Hypertext Markup Language (HTM1.). The companys products include QuickData Server, a parametric search engine for electronic component information, and Quickdata Miner, which transform information contained in PDF data sheets into a usable form. The mission or Genedax Inc., Portland, Ore. is to use the Web to increase designed ability to create and manage large, complex designs, to iron design ICLISC, and to improve access to intellectual property. The company plans to announce a product in the first quarter or the year. John Ott, vice president of sales and marketing, told Sprctmni that its products will be based on the operating systems and browsers developed by Microsott Corp., Redmond, Wash. Also, the company supports a collaborative Web site, that shows what the technology can do. The site includes a search engine based on AltaVista technology that searches the Web sites of companies related to design auto illation. Ott elaborated, We also have a free Internet locator server that lets people use Netmeeting a Microsoft product for remote sharing of computer desktops and a Web board where you can post questions and get answers. Other aspects of electronic design on the Webs have been slower in taking off than design and information management. But Transim Corp also bared in Portland, Ore, has taken a big step toward Web-based design tools. Its product, Websim, is an interface between a Web browser and Simples, the companys power-supply simulator. Websim allows designers, using Simplis, to simulate designs over the Internet. So rather than poring over data sheets and looking at ranges of values, designers can see actual waveforms, explained Ncls Gahbert, Transim president and chief executive officer.Transim is working with suppliers to set up component models so that designers can log on to the supplies Web rite, select parts for their power supply, enter setup or test conditions, and run the simulation on line. Users need nothing more than a Web browser. The simulation is run on Transims ranch of six strivers from Sun Microsystems. The company has teamed up with National Semiconductor Corp, Santa Clara, Calif., to provide this service for Nationals customers. The cost is on a per-use basis and is a minimal US $10. 附录C 翻译中文电子设计自动化关键字 电子设计自动化； 集成电路； VHDL语言；现场可编程门阵列在这个片上系统开始出现的时候，有三个问题一直困扰着集成电路设计者。首先就是缺乏一些东西即设计的硬件部件与软件部件之间缺少统一的语言。这样由于每一个芯片的逻辑闸门的数量超过了百万，因此，对设计正确性的验证瞬间比设计本身更加艰巨。另外，不仅仅是闸门数量问题，集成芯片的频率也在加大。因此，为了满足时间需要，做出一个不用反复设计的设计是遥远的目标。 由于已长期研究电子设计自动化，对于这方面的关注经常受到一些新建的公司抨击。那些公司是由几个志向远大启动资金缺乏的人领导。您说superlog？芯片系统由电路和软件组成运行。这样的系统一般包含一个嵌入的处理器核运行软件调制解调器。通常，芯片的功能被写在纸上后，硬件部件就交给了集成电路设计者，软件部件就给了程序设计者，在以后的某个闸门在合起来组在一起。芯片的一部分功能在逻辑闸门核晶体管被写入硬件描述语言-verilog语言或VHDL语言时结束。而另外一部分功能将在软件被描述在编程语言C或C+中结束。这种不同语言的使用给描述，仿制，调试集成电路的线路和软件的条理清晰方面都带来了很大的不便。 从工业角度上看我们相信是时候推出一种新的设计语言处理硬件和软件的问题，使系统从最初的设计规格直达最后的检验。加利福尼亚州的协同设计自动化公司的san jose发展了这种新型语言。在成立这个蒸蒸日上的企业前，合作者，现经营主任simon davidmann和peter flake已经得出了为满足片上系统发展现有语言的实用性。选为被发展的现有语言有C,C+,Java和Verilog。davidmann说一种设计语言必须满足三个需求。第一应该连接设计过程。第二应该使设计更为高效。第三应该由一种现存的方法演变而来。没有一种现存的方法满足这些需求，于是davidmann和flake决定发明一种新的协同设计语言，并命名为superlog。davidmann解释说“一个很自然的基准点就是连接verilog语言和C语言，从算法观点上来看，大多数verilog语言都是建立在C语言基础上的。”这时用比特和VHDL语言与Java语言将其连接起来。从Verilog andVHDL方面，superlog获得了设计中描述硬件方面的能力，例如顺序逻辑，组合逻辑和多值逻辑。从C和Java方面superlog又集成了动态处理器和其他软件编制。甚至像接口程序，活动网络路由协议和状态机等现阶段仍常被写在纸上的功能也能被新的语言描述了。为了处理已经存在的硬件描述或编程语言的遗留问题，superlog允许verilog语言和C语言模块输入并允许其直接使用。davidmann说这门语言推广到公共领域使用是非常重要的。公司已经开始和不同标准的组织合作工作达到其推广的目的。不被忽视是建立在语言上的设计工具套装软件的需要，目前协同设计公司已经和一些电子设计自动化公司确立了合作关系。其中magma 设计自动化公司，sente公司和viewlogic公司将发展建立的superlog上的工具。协同设计公司将继续为设计程序的前景开发新的产品。冲向终点的比赛并不是每一个人都相信我们需要新的语言。SystemC语言，一个建模平台，扩展了C/C+的容量和优势到硬件领域，已经被推荐为一个可选择的方案。许多像synopsys公司，coware公司，lucent技术公司和德州器具公司等大型权威的公司已经在开放性system C下联结在一起，开始创立他们下一代设计平台的版本。为了使system C重新运行，这个组提供了一个建模平台在他们的网址里免费下载。他们也希望他们的平台能成为实际的标准。据synopsys公司总经理兼系统级设计商业部副总裁