《数字电子技术》PPT课件

1、Figure 81 A 2-bit asynchronous binary counter. Open file F08-01 to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 82 Timing diagram for the counter of Figure 81. As in previous chapter

2、s, output waveforms are shown in green.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 83 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F08-03 to verify operation

3、.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 84 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Educatio

4、n, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 85 Four-bit asynchronous binary counter and its timing diagram. Open file F08-05 and verify the operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All r

5、ights reserved.,Figure 86 An asynchronously clocked decade counter with asynchronous recycling.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 87 Asynchronously clocked modulus-12 counter with asynchron

6、ous recycling.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 88 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connec

7、ted HIGH.),Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 89 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.),Thomas L. FloydD

8、igital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 810 74LS93 connected as a modulus-12 counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All righ

9、ts reserved.,Figure 811 A 2-bit synchronous binary counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 812 Timing details for the 2-bit synchronous counter operation (the propagation delays of both

10、flip-flops are assumed to be equal).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 813 Timing diagram for the counter of Figure 811.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Ed

11、ucation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 814 A 3-bit synchronous binary counter. Open file F08-14 to verify the operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Fig

12、ure 815 Timing diagram for the counter of Figure 814.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 816 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH

13、 are indicated by the shaded areas.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 817 A synchronous BCD decade counter. Open file F08-17 to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Cop

14、yright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 818 Timing diagram for the BCD decade counter (Q0 is the LSB).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserve

15、d.,Figure 819 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.),Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 820 Timing example f

16、or a 74HC163.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 821 The 74F162 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.),Thomas L. FloydDigital

17、Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 822 Timing example for a 74F162.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure

18、823 A basic 3-bit up/down synchronous counter. Open file F08-23 to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 824,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson

19、Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 825 The 74HC190 up/down synchronous decade counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 826 Timing example for a

20、 74HC190.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 827 General clocked sequential circuit.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New

21、Jersey 07458All rights reserved.,Figure 828 State diagram for a 3-bit Gray code counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 829 Examples of the mapping procedure for the counter sequence rep

22、resented in Table 87 and Table 88.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 830 Karnaugh maps for present-state J and K inputs.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Ed

23、ucation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 831 Three-bit Gray code counter. Open file F08-31 to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 832,Tho

24、mas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 833,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 834,Thoma

25、s L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 835 State diagram for a 3-bit up/down Gray code counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, Ne

26、w Jersey 07458All rights reserved.,Figure 836 J and K maps for Table 811. The control input, Y, is treated as a fourth variable.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 837 Three-bit up/down Gray

27、 code counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 838 Two cascaded counters (all J and K inputs are HIGH).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Up

28、per Saddle River, New Jersey 07458All rights reserved.,Figure 839 Timing diagram for the cascaded counter configuration of Figure 838.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 840 A modulus-100 co

29、unter using two cascaded decade counters.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 841 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and

30、divide-by-100 outputs.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 842,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights

31、reserved.,Figure 843 A divide-by-100 counter using two 74F162 decade counters.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 844 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note tha

32、t each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 845 Decoding of state 6 (110). Open file F0

33、8-45 to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 846 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Open file F08-46 to verify operation.,Thomas L. FloydDigita

34、l Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 847 A basic decade (BCD) counter and decoder.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights re

35、served.,Figure 848 Outputs with glitches from the decoder in Figure 847. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserve

36、d.,Figure 849 The basic decade counter and decoder with strobing to eliminate glitches.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 850 Strobed decoder outputs for the circuit of Figure 849.,Thomas L

37、. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 851 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 852 and 853.,Thomas L. FloydDigital Fundamental

38、s, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 852 Logic diagram of typical divide-by-60 counter using 74F162 synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).,Thomas L. FloydDigital

39、 Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 853 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2

40、006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 854 Functional block diagram for parking garage control.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 855

41、Logic diagram for modulus-100 up/down counter for automobile parking control.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 856 Parallel-to-serial data conversion logic.,Thomas L. FloydDigital Fundamen

42、tals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 857 Example of parallel-to-serial conversion timing for the circuit in Figure 856.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, Ne

43、w Jersey 07458All rights reserved.,Figure 858 The 74HC163 4-bit synchronous counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 859 Example of a failure that affects following counters in a cascaded

44、 arrangement.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 860 Example of a failure in a cascaded counter with a truncated sequence.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson E

45、ducation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 861,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 862,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Edu

46、cation, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 863 Traffic light control system block diagram.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 864 Sequence of traffic light s

47、tates.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 865 Block diagram of the sequential logic.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New

48、Jersey 07458All rights reserved.,Figure 866 State diagram for the traffic light control system.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 867 Sequential logic diagram.,Thomas L. FloydDigital Fundam

49、entals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 868 Input logic for the 2-bit Gray code counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserve

50、d.,Figure 869 The sequential logic.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 870 Block diagram of the complete traffic light control system.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006

51、by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 871 Comparison of asynchronous and synchronous counters.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 872 Note

52、 that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturers data book you are using. The devices shown are functionally the same and pin compatible with the same device types in other available CMOS and TTL IC families.,Thomas L. FloydDigi

53、tal Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 873,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 874,Thomas L. FloydDigita

54、l Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 875,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 876,Thomas L. FloydDigital

55、Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 877,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 878,Thomas L. FloydDigital Fu

56、ndamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 879,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 880,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 881,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,Figure 882,Thomas L. FloydDigital Fund