东芝电子可靠性测试

第第页东芝电子可靠性测试东芝电子牢靠性测试

[3]ReliabilityTesting

SemiconductorCompany

东芝电子牢靠性测试

Contents

1.WhatisReliabilityTesting1

1.11.21.31.41.5

SignificanceandPurposeofReliabilityTesting1BeforeTesting1ReliabilityTestMethods3FailureAssessmentCriteria9EquivalentelectrostaticDischargeTestCircuit10

1.6Latch-UpTest11

2.AcceleratedLifetimeTests12

2.12.22.32.42.52.62.7

Purpose12ConstantStressandStepStress13Temperature14TemperatureandHumidity19Voltage21TemperatureDifference22Current24

3.FailureRateEstimationMethods26

3.1Overview263.2EstimatingFailureRatesUsingAcceleratedLifetimeTests263.3EstimatingElectronicEquipmentFailureRatesUsingMIL-HDBK-21728

4.DetailedApplicationMethodsforReliabilityTesting

40

4.1DesignApprovalTestProcedures404.2ReliabilityMonitoringduringMassProduction41

东芝电子牢靠性测试

1.WhatisReliabilityTesting

1.1

SignificanceandPurposeofReliabilityTesting

Thepurposeofsemiconductordevicereliabilitytestingisprimarilytoensurethatshippeddevices,afterassemblyandadjustmentbythecustomer,e*hibitthedesiredlifetime,functionalityandperformanceinthehandsoftheenduser.

Nevertheless,thereareconstraintsoftimeandmoney.Becausesemiconductordevicesrequirealonglifetimeandlowfailurerate,totestdevicesunderactualusageconditionswouldrequireagreatamountoftesttimeande*cessivelylargesamplesizes.

Thetestingtimeisgenerallyshortenedthereforebyacceleratingvoltage,temperatureandhumidity.Inaddition,statisticalsamplingisused,takingintoaccountthesimilaritiesbetweenprocessanddesign,soastooptimizethenumberoftestsamples.

ToshibaperformsvariousreliabilitytestingduringnewproductdevelopmentfollowingthestagesshowninTable1.1.Inrecentyears,customerdemandforshorterdevelopment-to-shipmenttimes,andtheincreasingadvancementandcomple*ityofsemiconductordevices,hasmadefailureanalysise*tremelydifficult.Consequently,evaluationofbasicfailuremechanismsmustbegininthedevelopmentphase,dividingproductsintodifferenttestelementgroups(TEG),suchasprocessTEGanddesignTEG.

Toverifyproductreliability,variouslifetimeandenvironmenttests–aprocessreferredtoasdesignapprovaltesting(DAT)–ensurethattherequiredspecificationsandquality/reliabilitytargetsaremet.

Duringmassproduction,devicesaremadeunderstrictmanufacturingcontrolandscreeningtoeliminatethosewithapotentialforfailureandensurehigherreliability.Inaddition,initialinspectionsofproductcharacteristicsandperiodicreliabilitymonitoringareusedtoassesswhetherornottheproductqualitylevelremainshigh.Testsarecarriedoutwithhighefficiencyandfocusbyclassifyingassessmentlevelsaccordingtoproductinnovationandimportance,anddefiningtestitemsandassessmentstandardsaccordingly.

Thevariousreliabilitytestingdescribedabove,throughproblemidentificationandcorrectionateachphaseofdevicedevelopment,isusedtoprovidecustomerswithalevelofreliabilitythatensuressafeproductuse,andtomaintainandimprovereliabilityinthemanufacturingphaseaswell.

1.2BeforeTesting

Thefollowingpointsmustbeconsideredbeforeimplementingreliabilitytestsinordertosatisfytheobjectivesdescribedabove:

(1)Forwhatapplicationswillthedevicebeused?

(2)Inwhatpossibleenvironmentsandoperatingconditionswillthedevicebeused?

(3)Whatarethepossiblefailuremodesandmechanisms,andwhatkindofacceleratedstresstestingis

appropriate?

(4)Whatlevelofreliability(failurerate,fore*ample)doesthemarketrequireforthedevice?(5)Howlongisthedevicee*pectedtobeinservice?

东芝电子牢靠性测试

(6)Howdoesthedevicerateintermsofinnovationandimportance?Thesepointsmustbeconsideredwhen

determiningtests,stressconditionsandsamplesizes.

Thefollowingareacceleratedstresseswhichcanbeappliedtodevices.TheyaredescribedindetailinSection3.2.(1)Temperature

(2)Temperatureandhumidity(3)Voltage

(4)Temperaturedifference(5)Current

Thevarioustestsandtestconditionsforeachstresstypearedescribedinlatersections.

Animportantconsiderationinreliabilitytestingisthatthetestingmustcontributetotheappropriateevaluationandimprovementofsemiconductordevicereliability.

Itisthereforeimportanttoaccumulatereliabilitytestingresults,toperformdetailedfailureanalysiswhenfailureoccurs,andtofeedbacktheresultstothedesigndepartmentandmanufacturingprocess.

Table1.1MainStages,PurposesandContentsofReliabilityTesting

Material,processandbasicdesignverification

Toassesswhetherthe

material,processanddesignrulesenablesatisfactionofdesignedquality/reliabilityobjectivesanduser

specificationswhenappliedtotheproduct.

Toassesswhetherthe

productdesignsatisfiesthedesignedquality/reliabilityobjectivesanduserspecifications.

Content

Sample

SemiconductorDeviceDevelopment

ProcessTEGs,Metal(Al,Cu)electromigrationandstressmigration

functionblockevaluation,gateo*idefilmbreakdownvoltage

evaluation(TDDBtest,breakdownvoltagetest),MOSTEGs,etc.transistorhotcarrierinjection(HCI)effect,negativebiastemperatureinstability(NBTI)evaluation,failurerateformedium-andlarge-scaleintegratedcircuitsorproducts,newpackagemechanicalstrengthandenvironmenttest,etc.

Developmentverificationtests(lifetimetest,environmenttest,etc.),structuralanalysis

Products

Productreliabilityverification

ToassesswhethertheScreeningandreliabilitymonitoring(bySiprocessproductqualityandreliabilitygenerationandproductfamily)aremaintainedatprescribedlevels.

Products,TEGs

东芝电子牢靠性测试

1.3ReliabilityTestMethods

ReliabilitytestmethodsincludeTEGevaluation,inwhichspecialsetsofdevices(referredtoasatestelementgrouporTEG)arecreatedforeachfailurecause,andproductevaluation,wherebytheproductiscomprehensivelyevaluated.

1.3.1TEGEvaluation

TEGevaluationtargetsbasicfailuremechanisms.Inthismethod,asetofdevicesismanufacturedespeciallyfortheevaluationandanalysisofeachfailuremechanism.Themethodallowsdetailedevaluationandfailureanalysisoffailuremechanisms,andisveryeffectiveforquantifyinglimitsandaccelerationcapabilities.Table1.2showsane*ampleofTEGevaluationmethod.

Dependingontheobjective,TEGevaluationcanbeperformedeitherbyonwaferoranencapsulatedpackag.TEGevaluationhasfourmajorobjectives:

(1)DuringDAT(designapprovaltesting)ofnewtechnologyandproducts,itisusedtofindthemethodofeliminationforfailuremechanismsthataffectreliability.ThevariouskindsofTEGshowninTable1.2areusedtoevaluatefailuremechanismsattributabletotheprocessorthedesign.

(2)Clarifyfailuremechanismsinvolvedindefectsfoundduringtheproductevaluationphase.

(3)Formonitoringmanufacturingprocessparameters,monitorprocessqualitycontrolitemssuchasfilmthickness,filmshapeandcontamination,andfailureratesforeachprocessanddesignrule.

(4)DevelopTEGforeachfunctionblockandestimateproductreliabilitylifetimeandfailureratefromeachTEGcombination.

Inthismanner,theTEGcanbeusedforvariouspurposestopreciselyobtainappropriatedata.

东芝电子牢靠性测试

Table1.2TEGEvaluationE*amples

TEGStructureMOScapacitor

EvaluationTargetGateo*idefilmbreakdownIondrift

InterfacetrapProcessdamageVariationinmanufacturingconditions

Radiationeffect

DesignProcessParameterGatefilmthickness

GatefilmqualityO*idationmethodGatefilmmaterialElectrodematerialContaminationSurfaceareaShape

DimensionsGatesize(W/L)Gatefilmthickness

GatefilmqualityElectrodematerialContaminationPassivationmaterialShapeandstructure

IonimplantationconditionsMetallizationmaterial

MetallizationwidthMetallizationspace

Through-holediameter

ContactdiameterStep,holeshapeInterlayerinsulatingfilmPassivationMoldingresinShape,

dimensions,numberofelementsGatefilmthickness

GatefilmqualityInterlayerfilmquality

StressTemperatureVoltageElectricfieldCurrent

EvaluationMethodTDDB(constantcurrent,constantvoltage,stepstress)O*idefilmbreakdownvoltagetest

C-V(PulseC-V)DLTS(deeplevel

transientspectroscopy)

EvaluationParametersFailureratevs.timeO*idefilmbreakdownvoltage

QBD(o*idefilmbreakdownstaticcharge)

Electricfieldaccelerationcoefficient

ActivationenergyCO*(o*idefilmcapacitance)Failurerate

Vth(thresholdvoltagedegradation)

Id(draincurrentdegradation)

gm(gmdegradation)Voltageaccelerationcoefficient

ActivationenergySub-thresholdcharacteristics

FieldbreakdownvoltageResistancechangeFailureratevs.timeActivationenergyCurrentdensitydependenceOpenShort

MOStransistor

Hotcarriereffect

NegativebiasstabilityIondrift

InterfacetrapVariationinmanufacturingconditions

ProcessdamageShortchanneleffectFieldleak

TemperatureElectricfieldMechanicalstressCurrent

High-temperatureDCbiasing

Low-temperatureDCbiasing

ChargepumpingDCpulse

Multi-layermetallization(metal,diffusionlayer,interlayerinsulatingfilm)

StressMigration

ElectromigrationContactopen

InterlayerbreakdownvoltageCorrosion

TemperatureCurrentdensity

TemperaturegradientVoltageMechanicalstress

Temperatureandhumidity

Hightemperature,constantcurrenttestHigh-temperaturedischarge

TemperaturecycleReflowprocessHigh-temperature,high-humiditybiasingPressurecooker

Functionblock

ProcessmonitoringFailurerateestimationProcessapprovalHumidityresistance

TemperatureHigh-temperatureVoltagebiasing(DC,pulse)

Low-temperaturebiasing(DC,pulse)High-temperaturedischarge,etc.

Failureratevs.timeActivationenergyVoltageaccelerationStandbycurrentAC/DCparameters

东芝电子牢靠性测试

1.3.2ProductEvaluation

TEGevaluationproducesdetailedandwell-relateddataforeachfailuremechanism.However,defectsduetoinconsistenciesandthesynergyeffectresultingfromcombinationsoffailuremechanismsaredifficulttobedetected.Therefore,asacomplementtoTEGevaluation,acomprehensiveproductevaluationmustbeperformed.

Productreliabilitytestingispreferablyperformedunderactualfieldenvironmentconditionstothee*tentpossibleandmustalwaysberepeatable.Forthisreason,standardizedtestmethodsarepreferablyselectedtothee*tentpossible,andtestsshouldbeperformedaccordingtoapprovedsemiconductordevicestandards,suchasJIS,JEITA,MIL,IECandJEDEC.Table1.3showsrepresentativetestsforthesestandards.

ToshibaperformstestscommontosemiconductorproductsinaccordancewithtestmethodscompliantwithJIS,MIL,IEC,JEITAandJEDECstandards,asshowninTable1.4.Inaddition,testsforelectrostaticdischarge(ESD),latch-up,softerrorandotherconditionsareperformedunderfieldenvironmentalandclimaticconditions.

Table1.3ReliabilityTestStandards

JapanElectronicsandInformationTechnologyIndustriesAssociation(JEITTA)Standards

EIAJED-4701/001

EIAJED-4701/100EIAJED-4701/200EIAJED-4701/300EIAJED-4701/400EIAJED-4701/500

USMilitary(MIL)Standards

MIL-STD-202MIL-STD-883IEC60749IEC60068-1IEC60068-2JESD22JESD78

[General]

JISC00**(IEC60068-2)CECC90000CECC90100

TestMethodsforElectronicandElectricalPartsTestMethodsandProceduresforMicroelectronics

Semiconductordevices-MechanicalandclimatictestmethodsEnvironmentaltestingPart1:GeneralandguidanceEnvironmentaltestingPart2

SeriesTestMethodsICLatch-UpTest

EnvironmentarlandendurancetestmethodsforSemiconductorDevices(General)

EnvironmentarlandendurancetestmethodsforSemiconductorDevices(LifetimeTestI)EnvironmentarlandendurancetestmethodsforSemiconductorDevices(LifetimeTestII)EnvironmentarlandendurancetestmethodsforSemiconductorDevices(StrengthTestI)EnvironmentarlandendurancetestmethodsforSemiconductorDevices(StrengthTestII)EnvironmentarlandendurancetestmethodsforSemiconductorDevices(OtherTests)

InternationalElectrotechnicalCommission(IEC)Standards

JointElectronDevicesEngineering(JEDEC)Standards

JapaneseIndustrialStandards(JIS)

EnvironmentTestingMethods(ElectricityandElectronics)SeriesGeneralSpecificationMonolithicIntegratedCircuit

GeneralSpecificationDigitalMonolithicIntegratedCircuit

CENELECElectronicComponentsCommittee(CECC)

东芝电子牢靠性测试

Table1.4ProductReliabilityTestMethodE*amples(1/2)

东芝电子牢靠性测试

Table1.4ProductReliabilityTestE*amples(2/2)

Type

Standards

Test

DescriptionandTestConditions

EIAJED-4701

MIL-STD-883IEC60749

JESD22

VibrationtestEvaluateresistancetothevibrationappliedduring

transportandusage.Thetestincludesvariableandconstantfrequencyvibration;normallyvariableisused.

Normaltestconditions:

Constantfrequencyvibration:6020Hz,200m/s2inthreedirections,968Hineach

direction

Variablefrequencyvibration:100to2000Hz200m/s2inthreedirections,fourcyclesperdirection,fourminutespercycle

MechanicalShocktest

Evaluateresistancetotheshockappliedduringtransportandusage.Normaltestconditions:

Dependsondevicestructure.Withresinmoldeddevices,shockaccelerationof15,000m/s2isappliedthreetimesineachoffourdirections.Evaluateresistancetoconstantacceleration.Normaltestconditions:

Dependsondevicestructure.Withresinmoldeddevices,accelerationof200,000m/s2isappliedinsi*direction,eachforoneminuteEvaluatewhetherornotthestrengthoftheterminalareaissufficientfortheforceappliedduringinstallationandusage.Normaltestconditions:

Suspendaprescribedloadontothetipoftheleadtobendit90andback.Applytensileforce

inadirectionparalleltothelead.Theprescribedloadvariesaccordingtodevicestructure.

Solder-abilitytest

Evaluateterminalsolderability.Normaltestconditions:

Solderbathtemperature:230C,Dippingtime:5sec.

Solderbathtemperature:245C,Dippingtime:3sec.(lead-freesolder)

Sealingtest

Evaluatetheairtightnessoftheseal.Usebubblestodetectlargeleaks.Thistestissuitableformetallicandceramicpackages.

Evaluatetheresistancetocorrosioninasaltatmosphere.

Normaltestconditions:

35C,5%saltsolution,24hours

MechanicalTests

Constant

accelerationtest

―

Terminal

strengthtest

Salt

atmospheretest

东芝电子牢靠性测试

Standards

Type

TestDescriptionandTestConditions

EIAJED-4701―

MIL-STD-883IEC60749

―

Part33

JESD22A102-C

Pressurecookertest

Evaluateresistancewhenstoredunderpressureunderhightemperature,highhumidityforashortperiodoftime.Normaltestconditions:203to255kPa,RH=100%

Other

ElectrostaticEvaluatetheresistancetostaticelectricity.dischargetestNormaltestconditions:

Humanbodymodel:C=100pF,R=1.5k,

threedischarges

Machinemodel:C=200pF,R=0,onedischarge

Devicechargemodel

Latch-upstrengthtest

Evaluateresistancetolatch-up.Normaltestconditions:

Pulsecurrentinjectionmethod,current

applicationmethod,voltageapplicationmethod

PartA114-C/

Part27A115-A/

C101-C(Part28)

306―Part29JESD78

东芝电子牢靠性测试

1.4FailureAssessmentCriteria

Ingeneral,failuresaredividedintofatalfailuressuchasfunctionalfailure,opensandshorts,andotherfailuressuchasdegradationofelectricalcharacteristicsanddefectiveouterappearancewhichisdetectedasthefailureinvisualinspection.Toshibainprincipleassessesfailuresbasedonthesatisfactionofstandardsstipulatedinspecificationsforthedevice.

东芝电子牢靠性测试

1.5EquivalentElectrostaticDischargeTestCircuit

(1)HumanBodyModel(HBM)

Figure1.1EquivalentcircuitforHumanBodyModel(HBM)Test

(2)MachineModel(MM)

Figure1.2EquivalentcircuitforMachineModel(MM)Test

(3)

ChargedDeviceModel(CDM)

Figure1.3SchematicimagesofChargedDeviceModel(CDM)Test

(Left:RelayDischargeMethod,Right:FieldinducedMethod)

东芝电子牢靠性测试

1.6Latch-UpTest

Thefollowingshowstwolatch-uptestcircuitandtheresultsoftestimplementation.

(1)

TestCircuit

Figure1.4Latch-UpTestCircuit

东芝电子牢靠性测试

2.AcceleratedLifetimeTests

2.1Purpose

Withtheever-increasingrequirementsforpartanddevicereliability,theneedtoevaluateproductlifetimeandfailureratesquicklyisnowgreaterthanever.Reliabilitytestsareconductedundertestconditionsthatsimulatepotentialstressesappliedtosemiconductorcomponents.Dependingonthesituation,however,itmaytakeane*ceedinglylongtimeuntilfailureoccursorfailuremaynotoccurwithinthelimitedtesttime.Therefore,stressesbeyondthoseofactualoperatingconditionsareappliedtodevicestophysicallyand/orchronologicallyacceleratecausesofdegradation.Inthisway,devicelifetimeandfailureratescanbedetermined,andfailuremechanismscanbeanalyzed.Thistypeoftestisreferredtoasanacceleratedlifetimetest.Suchtestsareusedtoshortentheevaluationperiodandanalyzemechanismsindetail.

Theacceleratedlifetimetestisalsosometimesusedasaforceddegradationtesttoforciblyaccelerateaconstantstress.Itisalsosometimesusedasalimittestforacceleratingstresstodeterminealimitvalue.

Itisnecessarytobenotedthatfailuremechanismsinacceleratedtestsdiffersomewhatfromthosethatoccurunderactualusageconditions.Ingeneral,ifthedegradationmechanismissimple,accelerationisalsosimpleandlifetimeandfailureratescanbeestimatedrelativelyaccurately.Complicatedfailuremechanisms,however,aredifficulttosimulate,evenwhenbesteffortsaremadetoacceleratestressessimultaneously.Thisisbecausethedifferentstresseffectsareinterrelated.Therefore,analysisofaccelerationdataaswellasestimationoflifetimeandfailureratescanbedifficult.Whenperformingacceleratedlifetimetests,itisimportanttoselecttestconditionsthatresultinasfewfailuremechanismchangesaspossibleandthatminimizethenumberoffailuremechanisms,makingtestingeasyandsimple.

东芝电子牢靠性测试

2.2ConstantStressandStepStress

Therearetwotypesofacceleratedlifetimetesting:constantstressandstepstress.Inaconstantstresstest,thetime-dependentfailuredistributionofatestsamplesubjectedtoconstantstressatseveralstresslevelsisobserved.Inastepstresstest,stressisappliedtoatestsamplegraduallyinsteppedincrements,andthestepatwhichfailureoccursisobserved.

Atypicalconstantstresstestistheapplicationoftheconstantstressofpowerorambienttemperaturee*ceedingthema*imumrating.Weibulldistributionisoftenusedtoverifythatthefailuremodehasnotbeenchangedbythetest.ThevalidityoftheacceleratedtestisconfirmediftheshapeparametermoftheWeibulldistributionremainsunchangedbytheacceleratedstress.

Figure2.1showsWeibullplotswhenthepowerconsumptionofasilicontransistorischanged.Itisevidentfromthefigurethatparametermisconstantregardlessofthepowerconsumptionlevel.

Figure2.1WeibullDistributionandShapeParameterforTransistorAcceleratedLifetimeTest

Thissameresultshouldoccurinbothconstanttestsandsteptests.

Thus,asteptestproducesthefailuredatacorrespondingtoatleastoneconstantstress.Ifthefailuremodeofthepreviousstepisthesame,asteptestcanbyusedtodeterminethecriticaltemperatureforthecomponentandtoestimateitslifetime.Figure2.2showsane*ample.

东芝电子牢靠性测试

[3]ReliabilityTesting

Figure2.2FailureRateEstimationStepStress

2.3Temperature

Acceleratedlifetimetestingiscloselyassociatedwiththephysicsofthefailure.Thephysicalandchemicalreactionsofdevicedegradationaregenerallyusedaschemicalkinetics.Chemicalkineticsisabasicchemicalreactionmodelthatdescribesthetemperaturedependenceoffailures.ItisusedwiththeArrheniusmodel1inacceleratedlifetimetestingofsemiconductordevicesinrelationtotemperaturestress.

GivenachemicalreactionspeedK,theArrheniusequationcanbee*pressedas:

EaEa:Activationenergy(eV)K=Ae*p

k:Boltzmann’sconstant(8.61710－5[eV/K](1.38010－23[J/K]))

T:Absolutetemperature(K)

A:Constant

Iftheproduct’slifetimeendsatacertaindegradationa,thenlifetimeLcanbee*pressedasL=a/K.Givena/A=A’:

L=A'e*p

kT

东芝电子牢靠性测试

[3]ReliabilityTesting

Thisequatione*pressestherelationshipbetweentemperatureandlifetime.Ifthefailuremechanismisuniform,lnLand1/TcanbeplottedonastraightlineasshowninFigure2.3.Thatis,theaccelerationfromtemperatureT1toT2islnL1/lnL2.

lnL2LifetimelnL1

1/T11/T2

Temperature

(K)

Figure2.3RelationshipbetweenLifetimeandTemperature

GivenaccelerationcoefficientαandthelifetimetimesL1andL2attemperaturesT1andT2,respectively,theaccelerationcoefficientαcanbefoundusingthefollowingformula:

LEa:Activationenergy(eV)α=2=e*p112

k:Boltzmann’sconstant

temperature(K)T1,T2:Absolute

Figure2.4showstherelationshipbetweentheactivationenergyandtheaccelerationcoefficientateachtemperature.

ItcanbeseenfromtheArrheniusequationthattheaccelerationduetotemperaturechangesdrasticallywiththeactivationenergyEa.Figure2.5showstherelationshipbetweeneachactivationenergylevelandtheacceleratedcoefficientwhenthetemperaturedifferenceasaparameter.

东芝电子牢靠性测试

[3]ReliabilityTesting

Figure2.4RelationshipbetweenActivationEnergyandAccelerationCoefficient

Figure2.5RelationshipbetweenTemperatureandAccelerationCoefficientUsingActivation

EnergyasaParameter

Numeroussetsofdatahavebeendisclosedregardingtherelationshipbetweentemperatureandlifetimeorfailurerateofsemiconductordevices.Somee*amplesofdatafrome*perimentsconductedbyToshibaareasfollows:

(1)TemperatureAccelerationofIntermetallicFormationofBondingWire

Astemperaturerises,intermetallicalloybeginstoformatthejunctionofAuwireandtheAlusedonthepad,causingthecontactresistancetoincreaseandthecontacttoopen.Figure2.6showstherelationshipbetweenthetemperatureandlifetimefromtheresultsofhigh-temperaturestoragetesting.

Fromthelifetimevaluesatdifferenttemperatureconditions,itcanbeseenthattheactivationenergyisappro*imately1.0eV.

东芝电子牢靠性测试

Figure2.6TemperatureDependenceofFormationofIntermetallicAlloyinBondingWire

(2)TemperatureAccelerationonDifferentSemiconductorDevices

Variousdatahavebeenreportedfortherelationshipbetweenthetemperatureandfailurerateofsemiconductordevices.Figure2.7showsane*ampleofdataobtainedfromthistypeofe*periment.Thefiguregivestheaccelerationrateforeachdevice.

105104AccelerationRate

10

3

MOSIC

102101

BipIC

2.42.62.83.075

3.23.41/T103(K1)50

25

(C)

150125100

Temperature

Figure2.7E*ampleofDeviceTemperatureAcceleration

东芝电子牢靠性测试

Theactivationenergydiffersaccordingtothefailuremechanism.Table2.1showstypicalfailuremechanismsandactivationenergyvaluesobtainedfrome*perimentsperformedbyToshibaandotherorganizations.

Table2.1MainFailureMechanismsandActivationEnergyValues(E*amples)

FailureMode

FailureMechanism

Almetalelectromigration

Metalwiringfailure(open,short,corrosion)

AlmetalstressmigrationAu-AlalloygrowthCumetalelectromigrationAlcorrosion(moisturepenetration)

O*idefilmvoltagebreakdown(insulationbreakdown,O*idefilmbreakdownleakagecurrentincrease)hFEdegradationCharacteristicvaluefluctuation

Increasedleakagecurrent

IonmovementaccelerationduetomoistureDegradationbyNBTINaiondriveinSiO2

SlowtrappingofSi-SiO2interfaceInversionlayerformation

ActivationEnergy(ev)

0.4to1.20.5to1.40.85to1.10.8to1.00.6to1.20.3to0.90.80.5andup1.0to1.41.00.8to1.0

Note:Theabove-describedobtainedvaluesdifferaccordingtotheSiprocessgenerationand

detailedstructure.Thesevaluesreflectresultsactuallyobtainedaswellasresultsfromreportedcases.

ThemodeldescribedsofarwastheArrheniusmodelfortemperatureacceleration.AnotherfailuremodelistheEyringmodel.Thismodelconsiderstheeffectsof