VHDL与数字集成电路设计VHDL7-1

第七章：时间考虑2SynchronousTiming3LatchParametersDClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT4RegisterParametersDClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions5ClockUncertaintiesSourcesofclockuncertainty6ClockNonidealitiesClockskewSpatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitterTemporalvariationsinconsecutiveedgesoftheclocksignal;modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLVariationofthepulsewidthImportantforlevelsensitiveclocking7ClockSkewandJitterBothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJS8PositiveandNegativeSkew9PositiveSkewLaunchingedgearrivesbeforethereceivingedge10NegativeSkewReceivingedgearrivesbeforethelaunchingedge11TimingConstraintsMinimumcycletime:T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)12TimingConstraintsHoldtimeconstraint:t(c-q,cd)+t(logic,cd)>thold+Worstcaseiswhenreceivingedgearriveslate

Racebetweendataandclock13ImpactofJitter14LongestLogicPathin

Edge-TriggeredSystemsClkTTSUTClk-QTLMLatestpoint

oflaunchingEarliestarrival

ofnextcycleTJI+d15ClockConstraintsin

Edge-TriggeredSystemsIflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSU<T–TJI,1–TJI,2-dTc-q+TLM+TSU+d+2TJI<TSkewcanbeeitherpositiveornegative16ShortestPathClkTClk-QTLmEarliestpoint

oflaunchingDatamustnotarrive

beforethistimeClkTHNominal

clockedge17ClockConstraints

inEdge-TriggeredSystemsMinimumlogicdelayIflaunchingedgeisearlyandreceivingedgeislate:Tc-q+TLM–TJI,1<TH+TJI,2+dTc-q+TLM<TH+2TJI+d18ClockDistributionClockisdistributedinatree-likefashionH-tree19MorerealisticH-tree[Restle98]20TheGridSystemNorc-matchingLargepower2121164Clocking2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35nstskew=150pstcycle=3.3nsClockwaveformLocationofclockdriverondiepre-driverfinaldrivers2223ClockSkewinAlphaProcessor242Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)Clocking600MHz–0.35micronCMOSGlobalclockwaveform25SynchronousPipelinedDatapath26Self-TimedPipelinedDatapath27Hand-ShakingProtocolTwoPhaseHandshake28EventLogic–TheMuller-CElement292-PhaseHandshakeProtocol30Example:Self-timedFIFO31PLL-BasedSynchronization32PLLBlockDiagram33PhaseDetectorOutputbeforefilteringTransfer

characteristic34Phase-FrequencyDetector35PFDRes