EDA技术实用教程课后答案

xinxin1位半减器，然后用例化语句将它们连接起来，图4-20中hsuber是半减器，diff是(diff=x-y),s_outa是借位输出(s_out=1,x<y),sub_in是位输入f_outyinyOdiff,s_out:OUTSTD_LOGIC);sub_out,diff_out:OUTSTD_LOGIC);ARCHITECTUREfs1OFf_suberISdiff,s_out:OUTSTD_LOGIC);语句来完成此项设计y0,y1,y2,y3,y4,y5,y6,diff0,diff1,diff2,diff3:OUTSTD_LOGIC;diff4,diff5,diff6,diff7,sout:OUTSTD_LOGIC);ARCHITECTUREs8OFsuber_8ISCOMPONENTf_suber--sub_out,diff_out:OUTSTD_LOGIC);SIGNALa0,a1,a2,a3,a4,a5,a6:STD_u0:f_suberPORTMAP(xin=>x0,yin=>y0MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1);u2:MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2);u3:MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3);u4:MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4);u5:MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5);u6:MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6);u7:MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout);设计一个求补码的程序，输入数据是一个有符号的STD_LOGIC_VECTOR(7DOWNTO0));--补码输出ENuseieee.std_logic_useieee.std_logic_unsigneentityaddisport(a:instd_logic_vector(7downto0);b:instd_logic_vector(7downto0);ci:instd_locount:outstd_logic_vector(7downto0));endadd;architecturebhvofaddisbeginvariabledata:std_logic_vector(1downto0);variablec:std_logic;fornin0to7loopdataOUTSTD_LOGIC;--超过CNTH:OUTSTD_LOGIC_VECTOR(2DOWNTO0));--ARCHITECTUREbehavOFCNT10ISELSIFCLK'EVENTANDC给出含有异步清零和计数使能的16位二进制加减可控计数器的VHDL描述。ADD_SUB_LOAD_16;PROCESS(CLK,RST,ADD_EN,SUB_VARIABLECQI:STD_LOGIC_VECTOR(15ELSIFCLK'EVENTANDCIFCQI<16#FFFF#THENCQI:=C--计数--大于65535,计数值清零useieee.std_logic_useieee.std_logic_unsignetypestatesis(st0,st1,st2,st3,st4,st5);signalstx:states;ifrst='1'thenstx<=st0;q<="000";elsifclk'evecase(stx)iswhenst0=>q<="000";stx<=st1;whenst1=>q<="001";stx<=st2;whenst2=>q<="011";stx<=st3;whenst3=>q<="111";stx<=st4;whenst4=>q<="101";stx<=st5;whenst5=>q<="100";stx<=st0;whenothers=>stx<=st0;endcase;P_out:OUTSTD_LOGIC_VECTOR(4DOWNTO0);--P_out:o_e_out:OUTSTD_LOGIC);--o_e_out:奇校验输出位IFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿移位shift_cnt:="000";--o_e_out<=shift_Q(4)XORshift_Q(shift_cnt:=shift_cnt+1;--移位计数--计数范围(D=n):n-1~n/2取整(n=10:9\8\7\6--(n=11:10\9\8\7\6\5计数，前比后半周期多一个时钟)--解：实现图3-20(a)RTL图的OUT1:OUTSTD_LOGIC);ARCHITECTUREsxdlOFt3_12_aIS--解：实现图3-20(b)RTL图的ARCHITECTUREsxdlOFt3_12_bISABCD<=ABXORCD;WHENOTHERS=>NULL;ARCHITECTUREoneOFt3_12_cISCLK--------------------------------------------———SIGNALQ1:STD_LOGIC;--类似于在芯片内部定义ELSIFCLK'EVENTANDQ<=Q1;--将内部的暂存数据向端口输出ARCHITECTUREoneOFt3_12_dISQl-0D触发器程序(DFF_PRE_CLR.SIGNALQ1:STD_LOGIC;--类似于在芯片内部定ELSIFCLK'EVENTAND--IFEN='1'THENQ<=Q1;--将内部的暂存数据向端口输出ARCHITECTUREoneOFt3_12_eISSIGNALQ1:STD_LOGIC;--类似于在芯片内部定义一个数据的暂存节点BEGINELSIFCLK'EVENTANDQ<=Q1;--将内部的暂存数据向端口输出8-58-6S_out:OUTSTD_LOGIC);--序列输出位ARCHITECTUREbehavOFS_generatorISIFCLK'EVENTANDCLK='1'THuseieee.std_logic_useieee.std_logic_unsigneuseieee.std_lo